公开(公告)号：US20170141089A1

公开(公告)日：2017-05-18

申请号：US15345751

申请日：2016-11-08

Applicant: Infineon Technologies AG

Inventor： Daniel Domes ,  Reinhold Bayerer ,  Waleri Brekel

IPC: H01L25/11 ,  H05K7/20 ,  H01L23/64 ,  H01L23/367 ,  H01L23/495 ,  H02M7/00 ,  H01L23/552

CPC classification number: H01L25/115 ,  H01L23/3675 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/552 ,  H01L23/645 ,  H02M7/003 ,  H05K7/1432 ,  H05K7/209

Abstract: A multiplicity of power semiconductor switching elements of the same type parallel have a load current terminal for a load current input and a load current terminal for a load current output. At least one outer load current terminal and at least one inner load current terminal per load current direction include a load current input and a load current output. At least one contacting device for common electrical contacting all of the load current terminals of the same load current direction includes a load current input and a load current output. The contacting device includes a plurality of terminal tongues which are respectively fastened on an associated load current terminal. The geometry and/or profile of the terminal tongue of an outer load current terminal differs from the geometry and/or profile of the terminal tongue of an inner load current terminal of the same contacting device,

公开(公告)号：US10032755B2

公开(公告)日：2018-07-24

申请号：US15345751

申请日：2016-11-08

Applicant: Infineon Technologies AG

Inventor： Daniel Domes ,  Reinhold Bayerer ,  Waleri Brekel

IPC: H01L25/11 ,  H01L23/367 ,  H01L23/495 ,  H01L23/552 ,  H01L23/64 ,  H02M7/00 ,  H05K7/20 ,  H05K7/14

Abstract: A multiplicity of power semiconductor switching elements of the same type parallel have a load current terminal for a load current input and a load current terminal for a load current output. At least one outer load current terminal and at least one inner load current terminal per load current direction include a load current input and a load current output. At least one contacting device for common electrical contacting all of the load current terminals of the same load current direction includes a load current input and a load current output. The contacting device includes a plurality of terminal tongues which are respectively fastened on an associated load current terminal. The geometry and/or profile of the terminal tongue of an outer load current terminal differs from the geometry and/or profile of the terminal tongue of an inner load current terminal of the same contacting device.

公开(公告)号：US09659912B2

公开(公告)日：2017-05-23

申请号：US14830446

申请日：2015-08-19

Applicant: Infineon Technologies AG

Inventor： Reinhold Bayerer ,  Waleri Brekel

IPC: H01L25/07 ,  H01L23/498 ,  H01L23/053 ,  H01L23/00 ,  H01L23/373

CPC classification number: H01L25/072 ,  H01L23/053 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49844 ,  H01L23/49894 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49109 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A circuit arrangement includes at least two semiconductor chip having first and second load terminals that are each connected to one another, a first load current collecting conductor track, and also an external terminal electrically conductively connected thereto. For each of the semiconductor chips there is at least one electrical connection conductor electrically conductively connected to the first load terminal of the relevant semiconductor chip and also to the first load current collecting conductor track. The total inductance of all the connection conductors with which the first load terminal of the second of the semiconductor chips is connected to the first load current collecting conductor track has at least twice the inductance of that section of the first load current collecting conductor track which is formed between the second connection location of the first of the semiconductor chips and the second connection location of the second of the semiconductor chips.

公开(公告)号：US20160056132A1

公开(公告)日：2016-02-25

申请号：US14830446

申请日：2015-08-19

Applicant: Infineon Technologies AG

Inventor： Reinhold Bayerer ,  Waleri Brekel

IPC: H01L25/07 ,  H01L23/498 ,  H01L23/053 ,  H01L23/00

CPC classification number: H01L25/072 ,  H01L23/053 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49844 ,  H01L23/49894 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49109 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A circuit arrangement includes at least two semiconductor chip having first and second load terminals that are each connected to one another, a first load current collecting conductor track, and also an external terminal electrically conductively connected thereto. For each of the semiconductor chips there is at least one electrical connection conductor electrically conductively connected to the first load terminal of the relevant semiconductor chip and also to the first load current collecting conductor track. The total inductance of all the connection conductors with which the first load terminal of the second of the semiconductor chips is connected to the first load current collecting conductor track has at least twice the inductance of that section of the first load current collecting conductor track which is formed between the second connection location of the first of the semiconductor chips and the second connection location of the second of the semiconductor chips.

Abstract translation: 电路装置包括至少两个半导体芯片，其具有彼此连接的第一和第二负载端子，第一负载集流导体轨道以及与其电连接的外部端子。 对于每个半导体芯片，存在至少一个电连接导体，导电连接到相关半导体芯片的第一负载端子，并且还连接到第一负载集电导体轨道。 所述第二半导体芯片的第一负载端子与第一负载集电导体轨道连接的所有连接导体的总电感至少为第一负载集电导体轨道的该部分的电感的两倍 形成在第一半导体芯片的第二连接位置和第二半导体芯片的第二连接位置之间。