公开(公告)号：US20250141219A1

公开(公告)日：2025-05-01

申请号：US18931784

申请日：2024-10-30

Applicant: Infineon Technologies AG

Inventor： Mirko Scholz ,  Steffen Schumann ,  Gernot Langguth ,  Adrien Benoit Ille

IPC: H02H9/04

Abstract: In accordance with an embodiment, a device includes: a first supply rail; a second supply rail; an input/output terminal; an electrostatic discharge protection device comprising at least two stacked transistors coupled between the input/output terminal and a first one of the first supply rail or the second supply rail; and a trigger circuit coupled to the first supply rail and the second supply rail and configured to: detect an electrostatic discharge event at the input/output terminal based on a voltage of the first supply rail or a voltage of the second supply rail, and switch on the electrostatic discharge protection device in response to detecting the electrostatic discharge event.

公开(公告)号：US12278486B2

公开(公告)日：2025-04-15

申请号：US17584990

申请日：2022-01-26

Applicant: Infineon Technologies AG

Inventor： Gernot Langguth ,  Christoph Eichenseer ,  Stefan Kokorovic

IPC: H02H9/04 ,  H01L27/02 ,  H02H9/00

Abstract: A radio frequency integrated circuit (RFIC) device includes: a first RF input/output (I/O) terminal; a second RF I/O terminal, where the first and the second RF I/O terminals are configured to transmit or receive an RF signal; a capacitor coupled between the first and the second RF I/O terminals; a first coil coupled between the first and the second RF I/O terminals, where the first coil is configured to provide ESD protection to the capacitor during a first ESD event; and a fast transient ESD protection circuit coupled between the first and the second RF I/O terminals, where the fast transient ESD protection circuit is configured to provide ESD protection to the capacitor during a second ESD event different from the first ESD event, where a first rise time of the first ESD event is longer than a second rise time of the second ESD event.

公开(公告)号：US11967639B2

公开(公告)日：2024-04-23

申请号：US17648985

申请日：2022-01-26

Applicant: Infineon Technologies AG

Inventor： Gernot Langguth ,  Anton Boehm ,  Christian Cornelius Russ ,  Mirko Scholz

IPC: H01L29/74 ,  H01L27/02 ,  H01L29/06 ,  H02H9/04

CPC classification number: H01L29/7436 ,  H01L27/0259 ,  H01L29/0692 ,  H02H9/046 ,  H01L27/0285 ,  H01L27/0292 ,  H01L29/7408

Abstract: In accordance with an embodiment, a semiconductor device includes: an n-doped region disposed over an insulating layer; a p-doped region disposed over the insulating layer adjacent to the n-doped region, where an interface between the n-doped region and the p-doped region form a first diode junction; a plurality of segmented p-type anode regions disposed over the insulating layer, each of the plurality of segmented p-type anode regions being surrounded by the n-doped region, where a doping concentration of the plurality of segmented p-type anode regions is greater than a doping concentration of the p-doped region; and a plurality of segmented n-type cathode regions disposed over the insulating layer. Each of the plurality of segmented n-type cathode regions are surrounded by the p-doped region, where a doping concentration of the plurality of segmented n-type cathode regions is greater than a doping concentration of the n-doped region.

公开(公告)号：US20230238797A1

公开(公告)日：2023-07-27

申请号：US17584990

申请日：2022-01-26

Applicant: Infineon Technologies AG

Inventor： Gernot Langguth ,  Christoph Eichenseer ,  Stefan Kokorovic

IPC: H02H9/00 ,  H01L27/02 ,  H02H9/04

CPC classification number: H02H9/005 ,  H01L27/0255 ,  H02H9/046

Abstract: A radio frequency integrated circuit (RFIC) device includes: a first RF input/output (I/O) terminal; a second RF I/O terminal, where the first and the second RF I/O terminals are configured to transmit or receive an RF signal; a capacitor coupled between the first and the second RF I/O terminals; a first coil coupled between the first and the second RF I/O terminals, where the first coil is configured to provide ESD protection to the capacitor during a first ESD event; and a fast transient ESD protection circuit coupled between the first and the second RF I/O terminals, where the fast transient ESD protection circuit is configured to provide ESD protection to the capacitor during a second ESD event different from the first ESD event, where a first rise time of the first ESD event is longer than a second rise time of the second ESD event.

公开(公告)号：US11088542B1

公开(公告)日：2021-08-10

申请号：US16777195

申请日：2020-01-30

Applicant: Infineon Technologies AG

Inventor： Gernot Langguth ,  Adrien Benoit Ille ,  Steffen Schumann

IPC: H02H9/04 ,  H02H9/00 ,  H01L27/02

Abstract: In accordance with an embodiment, a method for electrostatic discharge (ESD) protection includes: dividing a voltage between a plurality of circuit nodes using a voltage divider circuit to form a divided voltage; compensating a temperature dependency of the divided voltage to form a temperature compensated divided voltage; monitoring the voltage between the plurality of circuit nodes using a transient detection circuit to form a transient detection signal; and activating a clamp circuit coupled between the plurality of circuit nodes based on the temperature compensated divided voltage and based on the transient detection signal.

公开(公告)号：US20210242678A1

公开(公告)日：2021-08-05

申请号：US16777292

申请日：2020-01-30

Applicant: Infineon Technologies AG

Inventor： Adrien Benoit Ille ,  Claudia Kupfer ,  Gernot Langguth

IPC: H02H9/04

Abstract: In accordance with an embodiment, a method for protecting a circuit includes: receiving a stress caused by an electrostatic discharge (ESD) event from a first node; limiting a current using a current limiting element coupled between the first node and a second node connected to the circuit; and limiting a voltage on the second node caused by the ESD event using a protection circuit including at least one MOS transistor having a load path coupled to the second node, where the at least one MOS transistor is disposed in a well, and a bias circuit coupled to a gate and a bulk connection of the at least one MOS transistor and a supply node.

公开(公告)号：US20190244953A1

公开(公告)日：2019-08-08

申请号：US15891133

申请日：2018-02-07

Applicant: Infineon Technologies AG

Inventor： Gernot Langguth

IPC: H01L27/02

CPC classification number: H01L27/0262 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0635 ,  H02M2001/0038

Abstract: In some examples, a device includes a first power supply node, an input-output node, and a second power supply node positioned between the first power supply node and the input-output node. The device also includes a protection element configured to block a parasitic flow of carriers between the first power supply node and the input-output node, wherein the parasitic flow of carriers is based on a voltage level of the second power supply node.