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公开(公告)号：US20180067888A1
公开(公告)日：2018-03-08
申请号：US15810556
申请日：2017-11-13
Applicant: Inphi Corporation
Inventor： Siddharth SHETH , Radhakrishnan L. NAGARAJAN
IPC: G06F13/42
CPC classification number: G06F13/42 , G06F13/364 , G06F13/4072 , G06F13/4282 , G06F15/7817 , H04L1/0003 , H04L25/03006
Abstract: The present invention provides an integrated system-on-chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The device has a signal processing block provided on the substrate member and coupled to the input/output block. The device has a driver module provided on the substrate member and coupled to the signal processing block. The device further includes a driver interface and coupled to the driver module and configured to be coupled to a silicon photonics device. In an example, a control block is configured to receive and send instruction(s) in a digital format to the communication block and is configured to receive and send signals in an analog format to communicate with the silicon photonics device.
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公开(公告)号：US20180032467A1
公开(公告)日：2018-02-01
申请号：US15730479
申请日：2017-10-11
Applicant: INPHI CORPORATION
Inventor： Siddharth SHETH , Radhakrishnan L. NAGARAJAN
IPC: G06F13/42
CPC classification number: G06F13/42 , G06F13/364 , G06F13/4072 , G06F13/4282 , G06F15/7807 , G06F15/7817 , H04L1/0003 , H04L25/03006 , H04L27/34
Abstract: The present invention provides an integrated system-on-chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The device has a signal processing block provided on the substrate member and coupled to the input/output block. The device has a driver module provided on the substrate member and coupled to the signal processing block. The device further includes a driver interface and coupled to the driver module and configured to be coupled to a silicon photonics device. In an example, a control block is configured to receive and send instruction(s) in a digital format to the communication block and is configured to receive and send signals in an analog format to communicate with the silicon photonics device.
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公开(公告)号：US20170127159A1
公开(公告)日：2017-05-04
申请号：US15403529
申请日：2017-01-11
Applicant: INPHI CORPORATION
Inventor： Radhakrishnan L. NAGARAJAN
IPC: H04Q11/00 , H04B10/516 , H04B10/80 , H04J14/02
CPC classification number: H04Q11/0005 , G02B6/122 , G02B2006/12097 , H04B10/5161 , H04B10/801 , H04J14/02 , H04Q11/0062 , H04Q2011/0016 , H04Q2011/0018 , H04Q2011/009 , H04Q2011/0096
Abstract: In an example, the present invention includes an integrated system on chip device. The device has a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol. In an example, the data input/output interface is configured for number of lanes numbered from four to one hundred and fifty. In an example, the SerDes block is configured to convert a first data stream of N into a second data stream of M such that each of the first data stream having a first predefined data rate at a first clock rate and each of the second data stream having a second predefined data rate at a second clock rate.
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公开(公告)号：US20160337046A1
公开(公告)日：2016-11-17
申请号：US15223326
申请日：2016-07-29
Applicant: INPHI CORPORATION
Inventor： Radhakrishnan L. NAGARAJAN
IPC: H04B10/80 , H04J14/02 , H04L29/08 , H04B10/54 , H04B10/516 , H04B10/69 , H04B10/40 , H04B10/556
CPC classification number: H04B10/801 , G02B6/00 , H04B10/40 , H04B10/5161 , H04B10/541 , H04B10/5561 , H04B10/69 , H04J14/02 , H04L69/324
Abstract: In an example, the present invention includes an integrated system on chip device. The device has a redundancy block is configured to add at least redundancy bit as a function of one or more data bits associated with data for data error detection and correction data. In an example, the driver module is coupled to the signal processing blocking using a uni-directional multi-lane bus configured with N lanes, whereupon N is greater than M such that a difference between N and M represents a redundant lane or lanes. The device also has a mapping block configured to associate the M lanes to a plurality of selected laser devices for a silicon photonics device.
Abstract translation: 在一个示例中，本发明包括集成片上系统设备。 该设备具有冗余块，被配置为至少将冗余位添加为与用于数据错误检测和校正数据的数据相关联的一个或多个数据位的函数。 在一个示例中，使用配置有N个通道的单向多通道总线将驱动器模块耦合到信号处理阻塞，因此N大于M，使得N和M之间的差异表示冗余车道或车道。 该装置还具有配置成将M通道与硅光子器件的多个选定的激光装置相关联的映射块。
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公开(公告)号：US20220285906A1
公开(公告)日：2022-09-08
申请号：US17191410
申请日：2021-03-03
Applicant: INPHI CORPORATION
Inventor： Xiaoguang HE , Radhakrishnan L. NAGARAJAN
Abstract: A laser device based on silicon photonics with an in-cavity power monitor includes a gain chip mounted on a silicon photonics substrate and configured to emit light in an active region bounded between a frontend facet with low reflectivity and a backend facet with anti-reflective characteristics. The laser device further includes a wavelength tuner formed with waveguides in the silicon photonics substrate optically coupled to the backend facet to receive light from the gain chip and configured to have a reflector with high reflectivity to reflect the light in an extended cavity formed with the frontend facet through which a laser with a tuned wavelength and amplified power is outputted. Additionally, the laser device includes a photodiode formed in the silicon photonics substrate and coupled to the waveguides in the extended cavity right in front of the reflector to measure power of light thereof.
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Patent Agency Ranking
公开(公告)号：US20220283360A1
公开(公告)日：2022-09-08
申请号：US17190867
申请日：2021-03-03
Applicant: INPHI CORPORATION
Inventor： Radhakrishnan L. NAGARAJAN , Mark PATTERSON
Abstract: An assembled electro-optical switch module includes a package substrate. Four optical socket members are disposed respectively to the package substrate. Each optical socket member includes four sockets closely packed in a row. Each socket has a recessed flat region with topside land grid array (LGA) interposer connected to bottom side solder bumps and a side notch opening aligned to an edge of the package substrate at the corresponding edge region. Sixteen optical modules in four sets are co-packaged in the package substrate. Each set has four optical modules respectively seated in the four sockets of each optical socket member with top side LGA interposer. Four clamp latch members are applied to clamp each of the four sets of optical modules in respective optical socket members. A data processor device with 51.2 Tbps data interface is disposed to the package substrate and electrically coupled to each of the sixteen optical modules.
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公开(公告)号：US20220255295A1
公开(公告)日：2022-08-11
申请号：US17168916
申请日：2021-02-05
Applicant: INPHI CORPORATION
Inventor： Xiaoguang HE , Radhakrishnan L. NAGARAJAN
IPC: H01S5/068 , H01S5/343 , H01S5/028 , H01S5/10 , H01S5/0234
Abstract: A high-power tunable laser includes a gain medium configured to emit light and amplify light intensity. The gain medium has a length equal to or greater than 1.5 mm between a backend and a frontend configured to be an output port for outputting light with amplified intensity. The high-power tunable laser further includes a wavelength tuner optically coupled to the backend to receive light from the gain medium and configured to tune wavelength for the light and have a high-reflectivity reflector to reflect the light with a tuned wavelength back to the gain medium.
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公开(公告)号：US20220013978A1
公开(公告)日：2022-01-13
申请号：US16922622
申请日：2020-07-07
Applicant: INPHI CORPORATION
Inventor： Xiaoguang HE , Radhakrishnan L. NAGARAJAN
Abstract: A method for improving wide-band wavelength-tunable laser. The method includes configuring a gain region between a first facet and a second facet and crosswise a PN-junction with an active layer between P-type cladding layer and N-type cladding layer. The method further includes coupling a light excited in the active layer and partially reflected from the second facet to pass through the first facet to a wavelength tuner configured to generate a joint interference spectrum with multiple modes separated by a joint-free-spectral-range (JFSR). Additionally, the method includes configuring the second facet to have reduced reflectivity for increasing wavelengths. Furthermore, the method includes reconfiguring the gain chip with an absorption layer near the active layer to induce a gain loss for wavelengths shorter than a longest wavelength associated with a short-wavelength side mode. Moreover, the method includes outputting amplified light at a basic mode via the second facet.
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19.发明申请公开(公告)号：US20200327093A1
公开(公告)日：2020-10-15
申请号：US16912535
申请日：2020-06-25
Applicant: INPHI CORPORATION
Inventor： Radhakrishnan L. NAGARAJAN
Abstract: The present invention provides an optical module for communicating a peer to peer transaction to transmit cryptocurrency. The optical module includes a substrate, a memory resource formed on the substrate, and a cryptocurrency wallet provided on the memory resource. Additionally, the optical module includes an optical communication block configured to generate an optical signal based on an electrical signal carrying a transaction message about an order of executing a plurality of transactions of cryptocurrency. The optical module includes an internal encryption block for encrypting the optical signal in the quadrature phases using an optical Quantum Key Generation encryption protocol. Furthermore, the optical module includes an application block to enable a cryptocurrency transaction and drive the optical communication block for sending encrypted optical signal via a direct-to-cloud interface to one or more entities in a cloud infrastructure and an external interface connecting the application block to a physical layer.
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公开(公告)号：US20200257050A1
公开(公告)日：2020-08-13
申请号：US16835093
申请日：2020-03-30
Applicant: INPHI CORPORATION
Inventor： Xiaoguang TU , Radhakrishnan L. NAGARAJAN , Masaki KATO
IPC: G02B6/293 , H04B10/2513 , G02B6/30 , G02B6/122 , G02B6/02
Abstract: An optical dispersion compensator integrated with a silicon photonics system including a first phase-shifter coupled to a second phase-shifter in parallel on the silicon substrate characterized in an athermal condition. The dispersion compensator further includes a third phase-shifter on the silicon substrate to the first phase-shifter and the second phase-shifter through two 2×2 splitters to form an optical loop. A second entry port of a first 2×2 splitter is for coupling with an input fiber and a second exit port of a second 2×2 splitter is for coupling with an output fiber. The optical loop is characterized by a total phase delay tunable via each of the first phase-shifter, the second phase-shifter, and the third phase-shifter such that a normal dispersion (>0) at a certain wavelength in the input fiber is substantially compensated and independent of temperature.
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