公开(公告)号：US09614508B1

公开(公告)日：2017-04-04

申请号：US14958701

申请日：2015-12-03

Applicant: Integrated Device Technology, Inc.

Inventor： Jagdeep Bal ,  Louis F. Poitras

IPC: H03L7/00 ,  H03K5/14 ,  H03K5/131

CPC classification number: H03K5/14 ,  H03K5/131

Abstract: A clock generator having deskewed outputs signals wherein a transit time of each of a plurality of traces coupled to the clock generator outputs are determined and the longest trace is identified as the trace having the longest transit time. A time delay is then added to an output clock signal at each of the clock generator outputs that are not coupled to the longest trace. The addition of the time delay for each of the clock generator outputs is effective in automatically deskewing the clock generator outputs.

公开(公告)号：US09553602B1

公开(公告)日：2017-01-24

申请号：US15076327

申请日：2016-03-21

Applicant: Integrated Device Technology, Inc.

Inventor： I-chang Wu ,  Jagdeep Bal

IPC: H03M1/12

CPC classification number: H03M1/12 ,  H03M1/0617 ,  H03M1/146 ,  H03M1/468

Abstract: Methods and apparatuses are described to convert analog signals to digital signals using a local charge averaging capacitor array (LCACA) in an analog-to-digital converter (ADC.) An apparatus includes a comparator. The comparator is configured with a first high input, a first low input, and is configure to receive a clock signal. A logic/latch block is configured to receive the clock signal and an output from the comparator. The logic/latch block is configured to output a control signal and a digital N-bit output signal. A local charge-averaging capacitor array (LCACA) is configured to receive the control signal and a reference voltage. An output of the LCACA is coupled to the first low input. The first LCACA is divided into a high sub-array and a low sub-array. The high sub-array is pre-charged to a high reference voltage and the low sub-array is pre-charged to a low reference voltage. The high reference voltage is greater than the low reference voltage. In operation, an analog signal is input to the first high input and the digital N-bit output signal is the digital conversion of the analog signal.

Abstract translation: 描述了使用模数转换器（ADC）中的局部电荷平均电容器阵列（LCACA）将模拟信号转换成数字信号的方法和装置。一种装置包括比较器。 比较器配置有第一高输入，第一低输入，并且被配置为接收时钟信号。 逻辑/锁存块配置为接收时钟信号和比较器的输出。 逻辑/锁存块被配置为输出控制信号和数字N位输出信号。 局部充电平均电容器阵列（LCACA）被配置为接收控制信号和参考电压。 LCACA的输出耦合到第一个低输入。 第一个LCACA分为高子阵列和低子阵列。 高子阵列预充电到高参考电压，低子阵列预充电到低参考电压。 高参考电压大于低参考电压。 在操作中，模拟信号被输入到第一高输入端，数字N位输出信号是模拟信号的数字转换。

公开(公告)号：US09553570B1

公开(公告)日：2017-01-24

申请号：US14566571

申请日：2014-12-10

Applicant: Integrated Device Technology, Inc.

Inventor： Jagdeep Bal

IPC: H03L7/06 ,  H03K5/1252 ,  H03B5/08 ,  H03B5/04

CPC classification number: H03K5/1252 ,  H03B5/04 ,  H03B5/1212 ,  H03B5/124 ,  H03B2200/009

Abstract: An integrated circuit to remove jitter from a clock signal includes an integrated circuit die. The integrated circuit die includes a signal comparator. The signal comparator is configured to determine a frequency difference between a jittery input clock signal and a correction signal. A digital low pass filter is coupled to receive and filter the frequency difference and to provide a filtered output signal. A free running crystal-less oscillator produces a reference signal. A fractional output divider is coupled to the free running crystal-less oscillator and the digital low pass filter. The fractional output divider utilizes the filtered output signal to establish a value to divide the reference signal by to obtain a clean output clock signal. The clean output clock signal is fed back to the signal comparator and is used as the correction signal.

Abstract translation: 用于从时钟信号中去除抖动的集成电路包括集成电路管芯。 集成电路管芯包括信号比较器。 信号比较器被配置为确定抖动输入时钟信号和校正信号之间的频率差。 数字低通滤波器被耦合以接收和滤除频率差并提供经滤波的输出信号。 自由运行的无晶体振荡器产生参考信号。 分数输出分频器耦合到自由运行的无晶体振荡器和数字低通滤波器。 分数输出分频器利用滤波后的输出信号建立一个值，以分配参考信号以获得干净的输出时钟信号。 干净的输出时钟信号反馈到信号比较器，并用作校正信号。