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公开(公告)号：US20190230049A1
公开(公告)日：2019-07-25
申请号：US16369889
申请日：2019-03-29
Applicant: Intel Corporation
Inventor： Kevin Clark , Scott J. Weber , Ravi Prakash Gutala , Aravind Raghavendra Dasu
IPC: H04L12/933 , H01L25/065
Abstract: This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.
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12.发明申请公开(公告)号：US20190044519A1
公开(公告)日：2019-02-07
申请号：US16020748
申请日：2018-06-27
Applicant: Intel Corporation
Inventor： Sean R. Atsatt , Scott J. Weber , Ravi Prakash Gutala , Aravind Raghavendra Dasu
IPC: H03K19/177
Abstract: An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die, such that the programmable logic fabric may include a first region of programmable logic fabric and a second region of programmable logic fabric. The first region of programmable logic fabric is configured to be programmed with a circuit design that operates on a first set of data. The integrated circuit may also include network on chip (NOC) circuitry disposed on a second integrated circuit die, such that the NOC circuitry is configured to communicate data between the first integrated circuit die and the second integrated circuit die.
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公开(公告)号：US12210873B2
公开(公告)日：2025-01-28
申请号：US18298278
申请日：2023-04-10
Applicant: Intel Corporation
Inventor： Eriko Nurvitadhi , Scott J. Weber , Ravi Prakash Gutala , Aravind Raghavendra Dasu
IPC: G06F9/30 , G05B19/05 , G06F15/78 , G06F30/34 , G06F30/343 , G06F30/347 , G06F30/39 , G06N3/02
Abstract: An integrated circuit device may include programmable logic circuitry on a first integrated circuit die and memory that includes compute-in-memory circuitry on a second die. The programmable logic circuitry may be programmed with a circuit design that operates on a first set of data. The compute-in-memory circuitry of the memory may perform an arithmetic operation using the first set of data from the programmable logic circuitry and a second set of data stored in the memory.
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公开(公告)号：US11442889B2
公开(公告)日：2022-09-13
申请号：US16146886
申请日：2018-09-28
Applicant: Intel Corporation
Inventor： Eriko Nurvitadhi , Scott J. Weber , Ravi Prakash Gutala , Aravind Raghavendra Dasu
Abstract: Methods and systems for dynamically reconfiguring a deep learning processor by operating the deep learning processor using a first configuration. The deep learning processor then tracking one or more parameters of a deep learning program executed using the deep learning processor in the first configuration. The deep learning processor then reconfigures the deep learning processor to a second configuration to enhance efficiency of the deep learning processor executing the deep learning program based at least in part on the one or more parameters.
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公开(公告)号：US11424744B2
公开(公告)日：2022-08-23
申请号：US17094612
申请日：2020-11-10
Applicant: Intel Corporation
Inventor： Kevin Clark , Scott J. Weber , James Ball , Ravi Prakash Gutala , Aravind Raghavendra Dasu
IPC: H03K19/1776 , G11C5/02 , G11C7/10 , H01L25/065
Abstract: An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces. The first die and the second die may be coupled using a multi-purpose interface that may allow communication between the first die and the second die. The multi-purpose interface may allow concurrent access to the base die by the programmable logic fabric and the configuration memory by using multiple channels over the multi-purpose interface.
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Patent Agency Ranking
公开(公告)号：US11223361B2
公开(公告)日：2022-01-11
申请号：US16882029
申请日：2020-05-22
Applicant: Intel Corporation
Inventor： Kevin Clark , Scott J. Weber , James Ball , Simon Chong , Ravi Prakash Gutala , Aravind Raghavendra Dasu , Jun Pin Tan
IPC: H03K19/1776 , H03K19/17704 , H03K19/17758 , H03K19/17768
Abstract: An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die and having configuration memory. The integrated circuit device may also include a base die that may provide memory and/or operating supporting circuitry. The first die and the second die may be coupled using a high-speed parallel interface. The interface may employ microbumps. The first die and the second die may also include controllers for the interface.
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公开(公告)号：US20210058085A1
公开(公告)日：2021-02-25
申请号：US17094612
申请日：2020-11-10
Applicant: Intel Corporation
Inventor： Kevin Clark , Scott J. Weber , James Ball , Ravi Prakash Gutala , Aravind Raghavendra Dasu
IPC: H03K19/1776 , G11C7/10 , H01L25/065 , G11C5/02
Abstract: An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces. The first die and the second die may be coupled using a multi-purpose interface that may allow communication between the first die and the second die. The multi-purpose interface may allow concurrent access to the base die by the programmable logic fabric and the configuration memory by using multiple channels over the multi-purpose interface.
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公开(公告)号：US10833679B2
公开(公告)日：2020-11-10
申请号：US16235984
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Kevin Clark , Scott J. Weber , James Ball , Ravi Prakash Gutala , Aravind Raghavendra Dasu
IPC: H03K19/177 , H01L25/00 , H03K19/1776 , G11C7/10 , H01L25/065 , G11C5/02
Abstract: An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces. The first die and the second die may be coupled using a multi-purpose interface that may allow communication between the first die and the second die. The multi-purpose interface may allow concurrent access to the base die by the programmable logic fabric and the configuration memory by using multiple channels over the multi-purpose interface.
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公开(公告)号：US20190103872A1
公开(公告)日：2019-04-04
申请号：US16146849
申请日：2018-09-28
Applicant: Intel Corporation
Inventor： Kevin Clark , Scott J. Weber , James Ball , Simon Chong , Ravi Prakash Gutala , Aravind Raghavendra Dasu
IPC: H03K19/177
Abstract: An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die and having configuration memory. The integrated circuit device may also include a base die that may provide memory and/or operating supporting circuitry. The first die and the second die may be coupled using a high-speed parallel interface. The interface may employ microbumps. The first die and the second die may also include controllers for the interface.
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公开(公告)号：US20190042529A1
公开(公告)日：2019-02-07
申请号：US16146886
申请日：2018-09-28
Applicant: Intel Corporation
Inventor： Eriko Nurvitadhi , Scott J. Weber , Ravi Prakash Gutala , Aravind Raghavendra Dasu
Abstract: Methods and systems for dynamically reconfiguring a deep learning processor by operating the deep learning processor using a first configuration. The deep learning processor then tracking one or more parameters of a deep learning program executed using the deep learning processor in the first configuration. The deep learning processor then reconfigures the deep learning processor to a second configuration to enhance efficiency of the deep learning processor executing the deep learning program based at least in part on the one or more parameters.
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