公开(公告)号：US20170177407A1

公开(公告)日：2017-06-22

申请号：US14973009

申请日：2015-12-17

Applicant: INTEL CORPORATION

Inventor： Guy Therien ,  Guy Sotomayor ,  Arijit Biswas ,  Michael D. Powell ,  Eric J. Dehaemer

IPC: G06F9/48 ,  G06F9/46 ,  G06F1/32 ,  G06F9/50

CPC classification number: G06F9/4856 ,  G06F1/3287 ,  G06F9/4418 ,  G06F9/461 ,  G06F9/4893 ,  G06F9/5094 ,  Y02D10/24 ,  Y02D10/32 ,  Y02D10/44

Abstract: Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).

公开(公告)号：US11853809B2

公开(公告)日：2023-12-26

申请号：US17857394

申请日：2022-07-05

Applicant: Intel Corporation

Inventor： Guy M. Therien ,  Michael D. Powell ,  Venkatesh Ramani ,  Arijit Biswas ,  Guy G. Sotomayor

IPC: G06F1/00 ,  G06F9/50 ,  G06F1/329 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/30

CPC classification number: G06F9/5083 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/3009 ,  G06F9/5033 ,  G06F9/5044 ,  G06F9/5094 ,  Y02D10/00

Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.

公开(公告)号：US20210263782A1

公开(公告)日：2021-08-26

申请号：US17173100

申请日：2021-02-10

Applicant: Intel Corporation

Inventor： Guy M. Therien ,  Michael D. Powell ,  Venkatesh Ramani ,  Arijit Biswas ,  Guy G. Sotomayor

IPC: G06F9/50 ,  G06F1/329 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/30

Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.

公开(公告)号：US20200241980A1

公开(公告)日：2020-07-30

申请号：US16779152

申请日：2020-01-31

Applicant: Intel Corporation

Inventor： Eric J. DeHaemer ,  Arijit Biswas ,  Reid J. Riedlinger ,  Ian M. Steiner

IPC: G06F11/20

Abstract: A multicore processor may include multiple processing cores that were previously designated as active cores and at least one processing core that was previously designated as a functional spare. The processor may include an interface to receive, during operation of the processor in an end-user environment, a request to change the designation of at least one of the processing cores. The processor may be to store, into a desired cores configuration data structure in response to the request, data representing a bitmask that reflects the requested change, and to execute a reset sequence. During the reset sequence, the processor may activate, dependent on the bitmask, a processing core previously designated as a functional spare, or may deactivate, dependent on the bitmask, a processing core previously designated as an active core. The processor may include a predetermined maximum number of active cores and a predetermined minimum number of functional spares.

公开(公告)号：US09058282B2

公开(公告)日：2015-06-16

申请号：US13732301

申请日：2012-12-31

Applicant: Intel Corporation

Inventor： Arijit Biswas

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0884 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0815 ,  G06F2212/1032

Abstract: A system, processor and method to monitor specific cache events and behavior based on established principles of quantized architectural vulnerability factor (AVF) through the use of a dynamic cache write policy controller. The output of the controller is then used to set the write back or write through mode policy for any given cache. This method can be used to change cache modes dynamically and does not require the system to be rebooted. The dynamic nature of the controller provides the capability of intelligently switching from reliability to performance mode and back as needed. This method eliminates the residency time of dirty lines in a cache, which increases soft errors (SER) resiliency of protected caches in the system and reduces detectable unrecoverable errors (DUE), while keeping implementation cost of hardware at a minimum.

Abstract translation: 通过使用动态缓存写策略控制器，基于量化架构漏洞因子（AVF）的已建立原则来监视特定缓存事件和行为的系统，处理器和方法。 然后，控制器的输出用于设置任何给定缓存的回写或写模式策略。 此方法可用于动态更改缓存模式，不需要重新启动系统。 控制器的动态特性提供了从可靠性到性能模式智能切换的能力，并根据需要返回。 该方法消除了缓存中脏线的驻留时间，这增加了系统中受保护高速缓存的软错误（SER）弹性，并降低了可检测的不可恢复错误（DUE），同时将硬件的实施成本降至最低。

公开(公告)号：US08990512B2

公开(公告)日：2015-03-24

申请号：US13664682

申请日：2012-10-31

Applicant: Intel Corporation

Inventor： Stanislav Shwartsman ,  Raanan Sade ,  Larisa Novakovsky ,  Arijit Biswas

IPC: G06F12/00

CPC classification number: G06F12/121 ,  G06F11/1064 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084 ,  G06F2212/1032 ,  G06T1/20

Abstract: A processor includes a core to execute instructions and a cache memory coupled to the core and having a plurality of entries. Each entry of the cache memory may include a data storage including a plurality of data storage portions, each data storage portion to store a corresponding data portion. Each entry may also include a metadata storage to store a plurality of portion modification indicators, each portion modification indicator corresponding to one of the data storage portions. Each portion modification indicator is to indicate whether the data portion stored in the corresponding data storage portion has been modified, independently of cache coherency state information of the entry. Other embodiments are described as claimed.

Abstract translation: 处理器包括执行指令的核心和耦合到核心并且具有多个条目的高速缓存存储器。 高速缓冲存储器的每个条目可以包括包括多个数据存储部分的数据存储部分，每个数据存储部分存储对应的数据部分。 每个条目还可以包括用于存储多个部分修改指示符的元数据存储器，每个部分修改指示符对应于数据存储部分之一。 每个部分修改指示符用于指示存储在相应的数据存储部分中的数据部分是否已被修改，而与条目的高速缓存一致性状态信息无关。 其他实施例被描述为所要求保护的。

公开(公告)号：US20240118942A1

公开(公告)日：2024-04-11

申请号：US18545912

申请日：2023-12-19

Applicant: Intel Corporation

Inventor： Guy M. Therien ,  Michael D. Powell ,  Venkatesh Ramani ,  Arijit Biswas ,  Guy G. Sotomayor

IPC: G06F9/50 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/30

CPC classification number: G06F9/5083 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/3009 ,  G06F9/5033 ,  G06F9/5044 ,  G06F9/5094 ,  Y02D10/00

Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.