公开(公告)号：US20190131975A1

公开(公告)日：2019-05-02

申请号：US16234212

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Sharath Raghava ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Harsha Gupta ,  James Ball ,  Kavitha Prasad ,  Sean R. Atsatt

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17796 ,  H04L41/5003 ,  H04L41/5019

Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

公开(公告)号：US20190108145A1

公开(公告)日：2019-04-11

申请号：US16211868

申请日：2018-12-06

Applicant: Intel Corporation

Inventor： Sharath Raghava ,  Dheeraj Subbareddy ,  Kavitha Prasad ,  Ankireddy Nalamalpu ,  Harsha Gupta

IPC: G06F13/16

Abstract: A central processing unit (CPU) may be directly coupled to an accelerator dual in-line memory module (DIMM) card that is plugged into a DIMM slot. The CPU may include a master memory controller that sends requests or offloads tasks to the accelerator DIMM card via a low-latency double data rate (DDR) interface. The acceleration DIMM card may include a slave memory controller for translating the received requests, a decoder for decoding the translated requests, control circuitry for orchestrating the data flow within the DIMM card, hardware acceleration resources that can be dynamically programmed to support a wide variety of custom functions, and input-output components for interfacing with various types of non-volatile and/or volatile memory and for connecting with other types of storage and processing devices.

公开(公告)号：US20240338397A1

公开(公告)日：2024-10-10

申请号：US18745711

申请日：2024-06-17

Applicant: Intel Corporation

Inventor： Jean Xu Yu ,  Haim Shmuel Barad ,  Harsha Gupta

IPC: G06F16/33 ,  G06F40/279 ,  G06T11/00

CPC classification number: G06F16/3344 ,  G06F40/279 ,  G06T11/00

Abstract: Methods, apparatus, systems, and articles of manufacture to determine a number of denoising iterations of model output generation are disclosed. An example apparatus includes at least one programmable circuit to execute a model to generate a plurality of outputs based on a text-based prompt, each of the plurality of outputs generated using different numbers of denoising iterations; generate an ordered set of the plurality of outputs based on the number of denoising iterations; determine a plurality of similarities between neighboring outputs in the ordered set of the plurality of outputs; and select a number of denoising iterations based on the plurality of similarities.

公开(公告)号：US20240028544A1

公开(公告)日：2024-01-25

申请号：US18478003

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Sharath Raghava ,  Dheeraj Subbareddy ,  Kavitha Prasad ,  Ankireddy Nalamalpu ,  Harsha Gupta

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4027 ,  G06F13/4282

Abstract: An integrated circuit device may include a first network on chip (NOC) circuit configured to receive a set of data and transfer the set of data to a first node of the first NOC circuitry. The first node is configured to transfer the set of data to a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device.

公开(公告)号：US11789883B2

公开(公告)日：2023-10-17

申请号：US16103709

申请日：2018-08-14

Applicant: Intel Corporation

Inventor： Sharath Raghava ,  Dheeraj Subbareddy ,  Kavitha Prasad ,  Ankireddy Nalamalpu ,  Harsha Gupta

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4027 ,  G06F13/4282

Abstract: An integrated circuit device may include a first network on chip (NOC) circuit configured to receive a set of data and transfer the set of data to a first node of the first NOC circuitry. The first node is configured to transfer the set of data to a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device.

公开(公告)号：US11700002B2

公开(公告)日：2023-07-11

申请号：US17556917

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Sharath Raghava ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Harsha Gupta ,  James Ball ,  Kavitha Prasad ,  Sean R. Atsatt

IPC: H04L12/28 ,  H03K19/17736 ,  H03K19/17796 ,  H04L41/5019 ,  H04L41/5003

CPC classification number: H03K19/17736 ,  H03K19/17796 ,  H04L41/5019 ,  H04L41/5003

Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

公开(公告)号：US20190050361A1

公开(公告)日：2019-02-14

申请号：US16103709

申请日：2018-08-14

Applicant: Intel Corporation

Inventor： Sharath Raghava ,  Dheeraj Subbareddy ,  Kavitha Prasad ,  Ankireddy Nalamalpu ,  Harsha Gupta

IPC: G06F13/40 ,  G06F13/42

Abstract: An integrated circuit device may include a first network on chip (NOC) circuit configured to receive a set of data and transfer the set of data to a first node of the first NOC circuitry. The first node is configured to transfer the set of data to a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device.