公开(公告)号：US12164462B2

公开(公告)日：2024-12-10

申请号：US17132663

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Ilya K. Ganusov ,  Ashish Gupta ,  Chee Hak Teh ,  Sean R. Atsatt ,  Scott Jeremy Weber ,  Parivallal Kannan ,  Aman Gupta ,  Gary Brian Wallichs

IPC: G06F15/78 ,  H04L45/60 ,  H04L49/109

Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.

公开(公告)号：US11960734B2

公开(公告)日：2024-04-16

申请号：US17033348

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Sean R Atsatt ,  Ilya K. Ganusov

IPC: G06F3/06 ,  G06N3/08 ,  H03K19/17724

CPC classification number: G06F3/0622 ,  G06F3/0655 ,  G06F3/0673 ,  G06N3/08

Abstract: Systems and methods described herein may relate to providing a dynamically configurable circuitry able to be programed using a microsector granularity. Furthermore, selective partial reconfiguration operations may be performed use write operations to write a new configuration over existing configurations to selectively reprogram a portion of programmable logic. A quasi-delay insensitive (QDI) shift register and/or control circuitry receiving data and commands from an access register disposed between portions of programmable logic may enable at least some of the operations described.

公开(公告)号：US20210326284A1

公开(公告)日：2021-10-21

申请号：US17359027

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Bee Yee Ng ,  Gaik Ming Chan ,  Ilya K. Ganusov

IPC: G06F13/28

Abstract: Systems and methods described herein may relate to burst sampling of an integrated circuit device. Such a system may include a first logic access block including a data register and a second logic access block including a memory column. The memory column may be configurable to operate as a First In, First Out (FIFO), user lookup table (LUT) mode, or as user random access memory (RAM). The memory column may store data sampled from the data register for any number of clock cycles and the data may be sampled at the speed of a clock of a device under test (DUT).