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    Changing cache ownership in clustered multiprocessor
    12.
    发明授权
    Changing cache ownership in clustered multiprocessor 有权

    公开(公告)号：US09690706B2

    公开(公告)日：2017-06-27

    申请号：US14668831

    申请日：2015-03-25

    Applicant: Intel Corporation

    Inventor： Rahul Pal ,  Ishwar Agarwal ,  Manoj K. Arora

    IPC: G06F12/08 ,  G06F12/084

    CPC classification number: G06F12/084 ,  G06F2212/2542 ,  G06F2212/271

    Abstract: Resolving coherency issues inherent in sharing distributed cache is described. A chip multiprocessor may include at least first and second processing clusters, each having multiple cores of a processor, multiple cache slices co-located with the multiple cores, and a memory controller (MC). The processor stores directory information in a memory coupled to the processor to indicate cluster cache ownership of a first address space to the first cluster. In response to a request to change the cluster cache ownership of the first address space, the processor may remap first lines of first cache slices, corresponding to the first address space, to second lines in second cache slices of the second cluster, and update the directory information (e.g., a state of the first cache lines) to change the cluster cache ownership of the first address space to the second cluster. One of the MCs may manage such updating of the directory.

    MULTICHIP PACKAGE LINK
    13.
    发明申请
    MULTICHIP PACKAGE LINK 有权
    多媒体包链接

    公开(公告)号：US20160283429A1

    公开(公告)日：2016-09-29

    申请号：US14669975

    申请日：2015-03-26

    Applicant: Intel Corporation

    Inventor： Mahesh Wagh ,  Zuoguo Wu ,  Venkatraman Iyer ,  Gerald S. Pasdast ,  Mark S. Birrittella ,  Ishwar Agarwal ,  Lip Khoon Teh ,  Su Wei Lim ,  Anoop Kumar Upadhyay

    IPC: G06F13/40 ,  G06F13/36 ,  G01R31/317

    CPC classification number: G06F13/4022 ,  G06F13/36 ,  G06F13/4068

    Abstract: A system-on-a-chip, such as a logical PHY, may be divided into hard IP blocks with fixed routing, and soft IP blocks with flexible routing. Each hard IP block may provide a fixed number of lanes. Using p hard IP blocks, where each block provides n data lanes, h=n*p total hard IP data lanes are provided. Where the system design calls for k total data lanes, it is possible that k≠h, so that [k/n] hard IP blocks provide h=n*p available hard IP data lanes. In that case, h−k lanes may be disabled. In cases where lane reversals occur, such as between hard IP and soft IP, bowtie routing may be avoided by the use of a multiplexer-like programmable switch within the soft IP.

    Abstract translation: 诸如逻辑PHY的片上系统可以被划分为具有固定路由的硬IP块和具有灵活路由的软IP块。 每个硬IP块可以提供固定数量的车道。 使用p硬IP块，其中每个块提供n个数据通道，h = n * p提供总硬IP数据通道。 在系统设计要求k个总数据通道的情况下，k≠h可以使得[k / n]硬IP块提供h = n * p可用的硬IP数据通道。 在这种情况下，h-k通道可能被禁用。 在发生通道反转的情况下，例如在硬IP和软IP之间，可以通过使用软IP内的多路复用器可编程开关来避免路由路由。

    Non-posted write transactions for a computer bus
    15.
    发明授权
    Non-posted write transactions for a computer bus 有权

    公开(公告)号：US11513979B2

    公开(公告)日：2022-11-29

    申请号：US17187271

    申请日：2021-02-26

    Applicant: Intel Corporation

    Inventor： Rajesh M. Sankaran ,  David J. Harriman ,  Sean O. Stalley ,  Rupin H. Vakharwala ,  Ishwar Agarwal ,  Pratik M. Marolia ,  Stephen R. Van Doren

    IPC: G06F13/16 ,  G06F13/42

    Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.

    System, apparatus and method for memory mirroring in a buffered memory architecture
    17.
    发明授权
    System, apparatus and method for memory mirroring in a buffered memory architecture 有权

    公开(公告)号：US11182313B2

    公开(公告)日：2021-11-23

    申请号：US16424875

    申请日：2019-05-29

    Applicant: Intel Corporation

    Inventor： Ishwar Agarwal ,  Theodros Yigzaw

    IPC: G06F12/00 ,  G06F13/16 ,  G06F12/0831 ,  G06F12/0868

    Abstract: In one embodiment, an apparatus includes: a first memory controller to control access to a first memory, the first memory controller including a memory mirroring circuit, in response to a memory write request from a first processor socket for which the first memory comprises a primary memory region, to cause data associated with the memory write request to be written to the first memory and to send a shadow memory write request to a second memory to cause the second memory to write the data into a secondary memory region; and a shadow memory table including a plurality of entries each to store an association between a primary memory region and a secondary memory region. The memory mirroring circuit may access the shadow memory table to identify the secondary memory region. Other embodiments are described and claimed.

    NON-POSTED WRITE TRANSACTIONS FOR A COMPUTER BUS
    18.
    发明申请
    NON-POSTED WRITE TRANSACTIONS FOR A COMPUTER BUS 有权

    公开(公告)号：US20210209037A1

    公开(公告)日：2021-07-08

    申请号：US17187271

    申请日：2021-02-26

    Applicant: Intel Corporation

    Inventor： Rajesh M. Sankaran ,  David J. Harriman ,  Sean O. Stalley ,  Rupin H. Vakharwala ,  Ishwar Agarwal ,  Pratik M. Marolia ,  Stephen R. Van Doren

    IPC: G06F13/16 ,  G06F13/42

    Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.

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