公开(公告)号：US12235792B2

公开(公告)日：2025-02-25

申请号：US18128852

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  Somvir Singh Dahiya ,  Mahesh Kumar P ,  Stephen H. Gunther ,  Sapumal Wijeratne ,  Mark Gallina

IPC: G06F9/50 ,  G06F1/324 ,  G06F9/48 ,  G06F15/78

Abstract: An apparatus and method for temperature-constrained frequency control and scheduling. For example, one embodiment of a processor comprises: a plurality of cores; power management circuitry to control a frequency of each core of the plurality of cores based, at least in part, on a temperature associated with one or more cores of the plurality of cores, the power management circuitry comprising: a temperature limit-driven frequency controller to determine a first frequency limit value based on a temperature of a corresponding core reaching a first threshold; frequency prediction hardware logic to predict a temperature-constrained frequency of the corresponding core based on the first frequency limit value and an initial frequency limit value; and performance determination hardware logic to determine a new performance value for the corresponding core based on the temperature-constrained frequency, the new performance value to be provided to a task scheduler.

公开(公告)号：US12141015B2

公开(公告)日：2024-11-12

申请号：US17127899

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Deepak S Kirubakaran ,  Ramakrishnan Sivakumar ,  Russell Fenger ,  Monica Gupta ,  Jianwei Dai ,  Premanand Sakarda ,  Guy Therien ,  Rajshree Chabukswar ,  Chad Gutierrez ,  Renji Thomas

IPC: G06F1/3287 ,  G06F1/3228

Abstract: A hardware and software coordinated processor power state policy (e.g., policy for C-state) that delivers optimal power state selection by taking in to account the performance and/or responsiveness needs of thread expected to be scheduled on the core entering idle, to achieve improved IPC and performance for cores running user critical tasks. The scheme provides the ability to deliver responsiveness gains for important and/or user-critical threads running on a system-on-chip. A power management controller coupled to the plurality of processing cores, wherein the power management controller receives a hint from an operating system indicative of a bias towards a power state or performance state for at least one of the processing cores of the plurality of processing cores based on a priority of a thread in context switch.

公开(公告)号：US20240213987A1

公开(公告)日：2024-06-27

申请号：US18089026

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  Jimin Zhang

IPC: H03K19/17736 ,  H03K19/17704 ,  H03K19/20

CPC classification number: H03K19/1774 ,  H03K19/17716 ,  H03K19/20

Abstract: Adaptive clock gating may provide improved power management of electronic devices. Clock gating may include removing a clock signal to state elements when those state elements are not being used, and the adaptive clock gating may provide improved clock gating for higher-level clock gates operating at increased frequencies. In an example, the adaptive clock gating may enable clock gating for higher-level clock gates within IP blocks that may be otherwise prevented from using clock gating due to timing requirements. The adaptive clock gating may be used to reduce power consumed by the clock distribution of IP blocks, thereby providing improved power efficiency. An adaptive clock gating circuit may include an IP clock frequency control unit with an adaptive clock gating logic circuit. The adaptive clock gating logic circuit may be used to selectively enable or disable high-level clock gates for the target IP based on a selected clock frequency.

公开(公告)号：US20240028101A1

公开(公告)日：2024-01-25

申请号：US18477823

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  David Pawlowski ,  Adwait Purandare ,  Ankush Varma

IPC: G06F1/3234 ,  G06F1/324 ,  G06F1/3206

CPC classification number: G06F1/3234 ,  G06F1/324 ,  G06F1/3206

Abstract: In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.

公开(公告)号：US11853144B2

公开(公告)日：2023-12-26

申请号：US17664083

申请日：2022-05-19

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  David Pawlowski ,  Adwait Purandare ,  Ankush Varma

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3206

CPC classification number: G06F1/3234 ,  G06F1/324 ,  G06F1/3206

Abstract: In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.

公开(公告)号：US20220188016A1

公开(公告)日：2022-06-16

申请号：US17558353

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  Virendra Vikramsinh Adsure ,  Taeyoung Kim ,  Chia-Hung S. Kuo ,  Deepak Gandiga Shivakumar ,  Amir Ali Radjai ,  Deepak Samuel Kirubakaran ,  Jianfang Zhu ,  Ivan Chen

IPC: G06F3/06

Abstract: An example apparatus includes processor circuitry to execute instructions to determine memory usage data associated with a user profile, determine an address hashing policy based on the memory usage data, and determine power states of memory channels based on the address hashing policy.

公开(公告)号：US11132201B2

公开(公告)日：2021-09-28

申请号：US16725041

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Ryan Carlson ,  Jianwei Dai

IPC: G06F9/30 ,  G06F9/38

Abstract: In an embodiment, a data path circuit includes: a plurality of pipeline stages coupled between an input of the data path circuit and an output of the data path circuit; and a first selection circuit coupled between a first pipeline stage and a second pipeline stage, the first selection circuit having a first input to receive an input to the first pipeline stage and a second input to receive an output of the first pipeline stage and controllable to output one of the input to the first pipeline stage and the output of the first pipeline stage. A bypass controller coupled to the data path circuit may control the first selection circuit based at least in part on an operating frequency of the data path circuit. Other embodiments are described and claimed.

公开(公告)号：US20210191725A1

公开(公告)日：2021-06-24

申请号：US16725041

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Ryan Carlson ,  Jianwei Dai

IPC: G06F9/38 ,  G06F9/30

Abstract: In an embodiment, a data path circuit includes: a plurality of pipeline stages coupled between an input of the data path circuit and an output of the data path circuit; and a first selection circuit coupled between a first pipeline stage and a second pipeline stage, the first selection circuit having a first input to receive an input to the first pipeline stage and a second input to receive an output of the first pipeline stage and controllable to output one of the input to the first pipeline stage and the output of the first pipeline stage. A bypass controller coupled to the data path circuit may control the first selection circuit based at least in part on an operating frequency of the data path circuit. Other embodiments are described and claimed.