公开(公告)号：US20200006302A1

公开(公告)日：2020-01-02

申请号：US16022677

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Andrew P. Collins ,  Jianyong Xie ,  Sujit Sharan

IPC: H01L25/16 ,  H01L23/48 ,  H01L23/64

Abstract: A package is disclosed. The package includes a base die. The base die includes voltage regulating circuitry and input and output (I/O) circuitry. The I/O circuitry surrounds the voltage regulating circuitry. The package also includes a top set of dies. The top set of dies includes a plurality of dies that include logic circuitry and a plurality of dies that include passive components. The plurality of dies that include passive components surround the plurality of dies that include logic circuitry. The plurality of dies that includes passive components is coupled to the logic circuitry and to the voltage regulating circuitry.

公开(公告)号：US20190304911A1

公开(公告)日：2019-10-03

申请号：US15937411

申请日：2018-03-27

Applicant: Intel Corporation

Inventor： Andrew Collins ,  Debendra Mallik ,  Mathew J. Manusharow ,  Jianyong Xie

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L21/48

Abstract: An embedded multi-die interconnect bridge (EMIB) die is configured with power delivery to the center of the EMIB die and the power is distributed to two dice that are interconnected across the EMIB die.

公开(公告)号：US11621223B2

公开(公告)日：2023-04-04

申请号：US16419374

申请日：2019-05-22

Applicant: Intel Corporation

Inventor： Andrew Collins ,  Sujit Sharan ,  Jianyong Xie

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00

Abstract: Embodiments herein relate to systems, apparatuses, or processes for an interconnect hub for dies that includes a first side and a second side opposite the first side to couple with three or more dies, where the second side includes a plurality of electrical couplings to electrically couple at least one of the three or more dies to another of the three or more dies to facilitate data transfer between at least a subset of the three or more dies. The three or more dies may be tiled dies.

公开(公告)号：US11462521B2

公开(公告)日：2022-10-04

申请号：US16022677

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Andrew P. Collins ,  Jianyong Xie ,  Sujit Sharan

IPC: H01L25/16 ,  H01L23/48 ,  H01L23/64 ,  H01L23/36

Abstract: A package is disclosed. The package includes a base die. The base die includes voltage regulating circuitry and input and output (I/O) circuitry. The I/O circuitry surrounds the voltage regulating circuitry. The package also includes a top set of dies. The top set of dies includes a plurality of dies that include logic circuitry and a plurality of dies that include passive components. The plurality of dies that include passive components surround the plurality of dies that include logic circuitry. The plurality of dies that includes passive components is coupled to the logic circuitry and to the voltage regulating circuitry.

公开(公告)号：US11276635B2

公开(公告)日：2022-03-15

申请号：US16636620

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Sujit Sharan ,  Kemal Aygun ,  Zhiguo Qian ,  Yidnekachew Mekonnen ,  Zhichao Zhang ,  Jianyong Xie

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/00

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.

公开(公告)号：US11222848B2

公开(公告)日：2022-01-11

申请号：US16634864

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Kemal Aygun ,  Zhiguo Qian ,  Jianyong Xie

IPC: H01L23/52 ,  H01L21/4763 ,  H01L23/538 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H01L23/31

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US11195805B2

公开(公告)日：2021-12-07

申请号：US15942092

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Andrew Collins ,  Sujit Sharan ,  Jianyong Xie

IPC: H01L23/66 ,  H01L23/522 ,  H01L23/538 ,  H01L23/528 ,  H01L25/00 ,  H01L21/48 ,  H01L25/16 ,  H01L23/48

Abstract: A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.

公开(公告)号：US12218063B2

公开(公告)日：2025-02-04

申请号：US16810192

申请日：2020-03-05

Applicant: Intel Corporation

Inventor： Jianyong Xie ,  Sujit Sharan ,  Huang-Ta Chen

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L23/64 ,  H01L25/18

Abstract: Embodiments disclosed herein include electronic packages with a bridge that comprise improved power delivery architectures. In an embodiment, a bridge comprises a substrate and a routing stack over the substrate. In an embodiment, the routing stack comprises first routing layers, where individual ones of the first routing layers have a first thickness, and a second routing layer, where the second routing layer has a second thickness that is greater than the first thickness.

公开(公告)号：US12205924B2

公开(公告)日：2025-01-21

申请号：US18112430

申请日：2023-02-21

Applicant: Intel Corporation

Inventor： Andrew Collins ,  Jianyong Xie

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528

Abstract: Apparatuses, devices and systems associated with semiconductor packages with chiplet and memory device coupling are disclosed herein. In embodiments, a semiconductor package may include a first chiplet, a second chiplet, and a memory device. The semiconductor package may further include an interconnect structure that couples the first chiplet to a first memory channel of the memory device and the second chiplet to a second memory channel of the memory device. Other embodiments may be described and/or claimed.

公开(公告)号：US20230299044A1

公开(公告)日：2023-09-21

申请号：US17698928

申请日：2022-03-18

Applicant: Intel Corporation

Inventor： Andrew P. Collins ,  Arghya Sain ,  Sujit Sharan ,  Jianyong Xie

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/19042 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/3025 ,  H01L2225/06537 ,  H01L2225/06586

Abstract: In one embodiment, a multi-die complex includes a mold material, first and second integrated circuit dies within the mold material, and one or more metal layers within the mold material. One or more passive electrical components, e.g., an inductor, a capacitor, or RF shielding, are formed at least partially within the metal layers.