公开(公告)号：US20200043190A1

公开(公告)日：2020-02-06

申请号：US16050724

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： JASON TANNER ,  KAI XIAO ,  JILL BOYCE ,  NARAYAN BISWAL ,  JEFFREY TRIPP

IPC: G06T7/593 ,  G06T7/13 ,  G06T7/136 ,  G06T5/00 ,  G06T15/00 ,  G06T1/20

Abstract: Embodiments described herein provide an apparatus comprising a processor to divide a first image projection into a plurality of regions, the plurality of regions comprising a plurality of points, determine an accuracy rating for the plurality of regions, and apply one of a first rendering technique to a first region in the plurality of regions when the accuracy rating for the first region in the plurality of regions fails to meet an accuracy threshold or a second rendering technique to the first region in the plurality of regions when the accuracy rating for the first region in the plurality of regions meets an accuracy threshold, and a memory communicatively coupled to the processor. Other embodiments may be described and claimed.

公开(公告)号：US20200043122A1

公开(公告)日：2020-02-06

申请号：US16050595

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： KAI XIAO ,  GOKCEN CILINGIR ,  JASON TANNER ,  SANG-HEE LEE ,  ATSUO KUWAHARA

IPC: G06T1/20 ,  G06T15/00 ,  G06T15/80 ,  G06F17/18

Abstract: Embodiments described herein provide an apparatus comprising a processor to divide a first projection into a plurality of regions, the plurality of regions comprising a plurality of pixels, detect errant visual content in a first region in the plurality of regions, determine a detail frequency rating for the first region, and apply one of a first rendering technique to the first region in the plurality of regions when the detail frequency rating for the first region in the plurality of regions fails to meet a detail frequency threshold or a second rendering technique to the first region in the plurality of regions when the detail frequency rating for the first region in the plurality of regions meets a detail frequency threshold. Other embodiments may be described and claimed.

公开(公告)号：US20190037689A1

公开(公告)日：2019-01-31

申请号：US15849043

申请日：2017-12-20

Applicant: Intel Corporation

Inventor： DAQIAO DU ,  ZHEN ZHOU ,  JUN LIAO ,  JAMES A. MCCALL ,  XIANG LI ,  KAI XIAO ,  ZHICHAO ZHANG

IPC: H05K1/02 ,  H05K1/05 ,  H05K1/11 ,  H01R12/72

Abstract: A system for a three-dimensional (“3D”) printed circuit board (“PCB”) to printed circuit board interface is provided. A first PCB includes first landing pads disposed on one or more edges of the first PCB. The first landing pads electrically couple to conductive pins or second landing pads disposed on a second PCB. The second landing pads may be disposed in a slot in the second PCB. The interface between the first landing pads and the second landing pads may provide various advantages over traditional PCB to PCB interfaces, such as, improved signal integrity, improved power integrity, increased contact density, decreased clock jitter, etc.