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公开(公告)号:US20190095281A1
公开(公告)日:2019-03-28
申请号:US15718031
申请日:2017-09-28
Applicant: Intel Corporation
Inventor: Marcin Pioch , Kapil Karkra , Piotr Wysocki , Slawomir Ptak
Abstract: According to various aspects, a storage system is provided, the storage system including a multiplicity of storage devices, and one or more processors configured to store user data on the multiplicity of storage devices, the stored user data being distributed among the multiplicity of storage devices together with redundancy data and with log data; generate a classification associated with the redundancy data and the log data to provide classified redundancy data and classified log data, and write the classified redundancy data and the classified log data on the respective storage device of the multiplicity of storage devices according to the classification associated therewith.
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公开(公告)号:US20190034120A1
公开(公告)日:2019-01-31
申请号:US15858067
申请日:2017-12-29
Applicant: Intel Corporation
Inventor: Mariusz Barczak , Dhruvil Shah , Kapil Karkra , Andrzej Jakowski , Piotr Wysocki
IPC: G06F3/06
Abstract: An embodiment of a semiconductor package apparatus may include technology to determine a stream classification for an access request to a persistent storage media, and assign the access request to a stream based on the stream classification. Other embodiments are disclosed and claimed.
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公开(公告)号:US12093563B2
公开(公告)日:2024-09-17
申请号:US17084301
申请日:2020-10-29
Applicant: Intel Corporation
Inventor: Kapil Karkra , Mariusz Barczak , Michal Wysoczanski , Sanjeev Trika , James Guilmart
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/061 , G06F3/0688 , G06F2212/7201
Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to manage access to a storage system that includes a first persistent storage device and a second persistent storage device, capture input/output telemetry for a workload on the storage system, determine one or more write reduction factors and one or more write invalidation factors for the workload based on the captured input/output telemetry, and allocate storage for the workload between the first persistent storage device and the second persistent storage device based on the one or more write reduction factors and the one or more write invalidation factors. Other embodiments are disclosed and claimed.
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公开(公告)号:US20220107733A1
公开(公告)日:2022-04-07
申请号:US17551755
申请日:2021-12-15
Applicant: Intel Corporation
Inventor: Sanjeev Trika , Kapil Karkra , Mariusz Barczak
Abstract: An embodiment of an electronic apparatus may comprise a processor, memory communicatively coupled to the processor, and circuitry communicatively coupled to the processor and the memory to determine a group of available types of persistent memory devices and a set of characteristics associated with each type of persistent memory device of the group of available types of persistent memory devices, determine of a set of requirements for a storage system, and determine a deployment configuration for the storage system with a lowest storage acquisition cost based on the group of available types of persistent memory devices, the sets of characteristics, and the set of requirements. Other embodiments are disclosed and claimed.
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公开(公告)号:US11137916B2
公开(公告)日:2021-10-05
申请号:US16021722
申请日:2018-06-28
Applicant: Intel Corporation
Inventor: Michael Mesnier , Kapil Karkra , Piotr Wysocki , Jonathan Hughes , Brennan Watt , Sanjeev Trika , Anand Ramalingam
IPC: G06F3/06
Abstract: An embodiment of a semiconductor apparatus may include technology to selectively determine a set of data for background refresh based at least in part on host-provided information, and refresh the determined set of data on a persistent storage media as a background operation. Other embodiments are disclosed and claimed.
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公开(公告)号:US20190050161A1
公开(公告)日:2019-02-14
申请号:US16014550
申请日:2018-06-21
Applicant: Intel Corporation
Inventor: Piotr Wysocki , Slawomir Ptak , Kapil Karkra , Marcin Pioch
Abstract: Embodiments of the present disclosure may relate to a data storage apparatus that may include a redundancy logic to determine recovery data based on data in a storage region buffer; and a storage region controller to schedule a first set of non-volatile memory (NVM) dies in a first solid state drive (SSD) to be in a non-deterministic (ND) state or a deterministic (D) state, schedule a second set of NVM dies in a second SSD to be in a ND state or a D state, issue a first write command to write the data to the first set of NVM dies when the first set of NVM dies are in the ND state, and issue a second write command to write the recovery data to the second of NVM dies when the second set of NVM dies are in the ND state. Other embodiments may be described and/or claimed.
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公开(公告)号:US20190042355A1
公开(公告)日:2019-02-07
申请号:US16018448
申请日:2018-06-26
Applicant: Intel Corporation
Inventor: Slawomir Ptak , Piotr Wysocki , Kapil Karkra , Sanjeev N. Trika
Abstract: An apparatus may include a storage driver, the storage driver coupled to a processor, to a non-volatile random access memory (NVRAM), and to a redundant array of independent disks (RAID), the storage driver to: receive a memory write request from the processor for data stored in the NVRAM; calculate parity data from the data and store the parity data in the NVRAM; and write the data and the parity data to the RAID without prior storage of the data and the parity data to a journaling drive. In embodiments, the storage driver may be integrated with the RAID. In embodiments, the storage driver may write the data and the parity data to the RAID by direct memory access (DMA) of the NVRAM.
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公开(公告)号:US20170123921A1
公开(公告)日:2017-05-04
申请号:US14931730
申请日:2015-11-03
Applicant: Intel Corporation
Inventor: Slawomir Ptak , Sanjeev N. Trika , Piotr Wysocki , Kapil Karkra , Rajib Ghosal
CPC classification number: G06F11/1096 , G06F3/061 , G06F3/0619 , G06F3/064 , G06F3/0659 , G06F3/0689
Abstract: An apparatus includes a plurality of drives configured as a redundant array of independent disks (RAID) and drive array controller logic to: calculate a first partial parity log (PPL) value for a first write operation that targets a first active stripe of the plurality of drives; store the first PPL value in a first pre-allocated portion of the plurality of drives that depends on a first number associated with the first active stripe; calculate a second PPL value for a second write operation that targets a second active stripe of the plurality of drives; and store the second PPL value in a second pre-allocated portion of the plurality of drives that depends on a second number associated with the second active stripe.
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