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公开(公告)号:US20210117123A1
公开(公告)日:2021-04-22
申请号:US17133830
申请日:2020-12-24
Applicant: Intel Corporation
Inventor: Andrzej Jakowski , Revanth Rajashekar
IPC: G06F3/06
Abstract: An embodiment of an electronic apparatus may include a substrate, a local memory coupled to the substrate, and logic coupled to the substrate and the local memory, the logic to locally manage a rebuild of data on a persistent storage media in response to a rebuild initiation command, and utilize peer-to-peer communication to transfer data from a member drive to the local memory. Other embodiments are disclosed and claimed.
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公开(公告)号:US10402338B2
公开(公告)日:2019-09-03
申请号:US15477037
申请日:2017-04-01
Applicant: Intel Corporation
Inventor: Andrzej Jakowski , Kapil Kumar Karkra
IPC: G06F12/08 , G06F12/0897 , G06F12/02 , G06F12/0804 , G06F12/0811 , G06F12/121
Abstract: In one embodiment, a processor comprises a processing core; and a cache controller to send a plurality of write requests to a cache storage device to store cache lines of a stream block, the plurality of write requests each including a stream identifier of the stream block, wherein a capacity of the stream block is equal to a capacity of an erase block of the cache storage device and wherein the erase block is dedicated to storing cache lines of the stream block; determine to evict the stream block from the cache storage device based upon a determination that space is not available in the cache storage device to cache data received from a first storage device; and send a deallocation request to the cache storage device to deallocate all cache lines of the stream block to enable the cache storage device to erase the erase block.
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公开(公告)号:US10146688B2
公开(公告)日:2018-12-04
申请号:US15393863
申请日:2016-12-29
Applicant: Intel Corporation
Inventor: Maciej Kaminski , Andrzej Jakowski , Piotr Wysocki
IPC: G06F12/08 , G06F12/0811 , G06F12/0846 , G06F12/128 , G06F12/0871
Abstract: An embodiment of a cache apparatus may include a first cache memory, a second cache memory, and a cache controller communicatively coupled to the first cache memory and the second cache memory to allocate cache storage for clean data from one of either the first cache memory or the second cache memory, and allocate cache storage for dirty data from both the first cache memory and the second cache memory. Other embodiments are disclosed and claimed.
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公开(公告)号:US20190034120A1
公开(公告)日:2019-01-31
申请号:US15858067
申请日:2017-12-29
Applicant: Intel Corporation
Inventor: Mariusz Barczak , Dhruvil Shah , Kapil Karkra , Andrzej Jakowski , Piotr Wysocki
IPC: G06F3/06
Abstract: An embodiment of a semiconductor package apparatus may include technology to determine a stream classification for an access request to a persistent storage media, and assign the access request to a stream based on the stream classification. Other embodiments are disclosed and claimed.
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公开(公告)号:US20180089082A1
公开(公告)日:2018-03-29
申请号:US15280650
申请日:2016-09-29
Applicant: Intel Corporation
Inventor: Andrzej Jakowski , Maciej Kaminski
IPC: G06F12/0808 , G06F3/06 , G06F12/128 , G06F12/0806
CPC classification number: G06F3/0685 , G06F12/0246 , G06F12/0804 , G06F12/0868 , G06F12/12
Abstract: In one embodiment, a request to access a first storage location of a storage device may be received, wherein the storage device comprises a data storage and a cache. The cache may be accessed to obtain data for one or more second storage locations of the storage device, wherein the data for the one or more second storage locations has not been written to the data storage, and wherein the first storage location and the one or more second storage locations are located near each other on the data storage. The data storage may then be accessed in response to the request to access the first storage location of the storage device. The data storage may also be accessed to write the data for the one or more second storage locations obtained from the cache.
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公开(公告)号:US10331385B2
公开(公告)日:2019-06-25
申请号:US15280650
申请日:2016-09-29
Applicant: Intel Corporation
Inventor: Andrzej Jakowski , Maciej Kaminski
IPC: G06F12/08 , G06F3/06 , G06F12/02 , G06F12/0804 , G06F12/0868 , G06F12/12
Abstract: In one embodiment, a request to access a first storage location of a storage device may be received, wherein the storage device comprises a data storage and a cache. The cache may be accessed to obtain data for one or more second storage locations of the storage device, wherein the data for the one or more second storage locations has not been written to the data storage, and wherein the first storage location and the one or more second storage locations are located near each other on the data storage. The data storage may then be accessed in response to the request to access the first storage location of the storage device. The data storage may also be accessed to write the data for the one or more second storage locations obtained from the cache.
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公开(公告)号:US20180285282A1
公开(公告)日:2018-10-04
申请号:US15477037
申请日:2017-04-01
Applicant: Intel Corporation
Inventor: Andrzej Jakowski , Kapil Kumar Karkra
IPC: G06F12/0891 , G06F12/0897
CPC classification number: G06F12/0897 , G06F12/0246 , G06F12/0804 , G06F12/0811 , G06F12/121 , G06F2212/1024 , G06F2212/222 , G06F2212/7205
Abstract: In one embodiment, a processor comprises a processing core; and a cache controller to send a plurality of write requests to a cache storage device to store cache lines of a stream block, the plurality of write requests each including a stream identifier of the stream block, wherein a capacity of the stream block is equal to a capacity of an erase block of the cache storage device and wherein the erase block is dedicated to storing cache lines of the stream block; determine to evict the stream block from the cache storage device based upon a determination that space is not available in the cache storage device to cache data received from a first storage device; and send a deallocation request to the cache storage device to deallocate all cache lines of the stream block to enable the cache storage device to erase the erase block.
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公开(公告)号:US20180189178A1
公开(公告)日:2018-07-05
申请号:US15393863
申请日:2016-12-29
Applicant: Intel Corporation
Inventor: Maciej Kaminski , Andrzej Jakowski , Piotr Wysocki
IPC: G06F12/0811 , G06F12/0846 , G06F12/128 , G06F12/0871
CPC classification number: G06F12/0871 , G06F11/1076 , G06F12/0804 , G06F12/0851 , G06F12/128 , G06F2212/1016 , G06F2212/222 , G06F2212/283 , G06F2212/286 , G06F2212/604
Abstract: An embodiment of a cache apparatus may include a first cache memory, a second cache memory, and a cache controller communicatively coupled to the first cache memory and the second cache memory to allocate cache storage for clean data from one of either the first cache memory or the second cache memory, and allocate cache storage for dirty data from both the first cache memory and the second cache memory. Other embodiments are disclosed and claimed.
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