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    FLATTENING PORTAL BRIDGE
    11.
    发明申请
    FLATTENING PORTAL BRIDGE 有权

    公开(公告)号：US20210232522A1

    公开(公告)日：2021-07-29

    申请号：US17136347

    申请日：2020-12-29

    Applicant: Intel Corporation

    Inventor： David J. Harriman ,  Reuven Rozic ,  Maxim Dan ,  Prashant Sethi ,  Robert E. Gough ,  Shanthanand Kutuva Rabindranath

    IPC: G06F13/40 ,  G06F13/42

    Abstract: A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.

    PCI EXPRESS TUNNELING OVER A MULTI-PROTOCOL I/O INTERCONNECT
    12.
    发明申请
    PCI EXPRESS TUNNELING OVER A MULTI-PROTOCOL I/O INTERCONNECT 审中-公开

    公开(公告)号：US20200042482A1

    公开(公告)日：2020-02-06

    申请号：US16543934

    申请日：2019-08-19

    Applicant: INTEL CORPORATION

    Inventor： David J. Harriman ,  Maxim Dan

    IPC: G06F13/40 ,  G06F13/42 ,  G06F13/38

    Abstract: Described are embodiments of methods, apparatuses, and systems for PCIe tunneling across a multi-protocol I/O interconnect of a computer apparatus. A method for PCIe tunneling across the multi-protocol I/O interconnect may include establishing a first communication path between ports of a switching fabric of a multi-protocol I/O interconnect of a computer apparatus in response to a peripheral component interconnect express (PCIe) device being connected to the computer apparatus, and establishing a second communication path between the switching fabric and a PCIe controller. The method may further include routing, by the multi-protocol I/O interconnect, PCIe protocol packets of the PCIe device from the PCIe device to the PCIe controller over the first and second communication paths. Other embodiments may be described and claimed.

    PCI EXPRESS TUNNELING OVER A MULTI-PROTOCOL I/O INTERCONNECT
    13.
    发明申请
    PCI EXPRESS TUNNELING OVER A MULTI-PROTOCOL I/O INTERCONNECT 审中-公开

    公开(公告)号：US20180357195A1

    公开(公告)日：2018-12-13

    申请号：US15942922

    申请日：2018-04-02

    Applicant: INTEL CORPORATION

    Inventor： David J. Harriman ,  Maxim Dan

    IPC: G06F13/40 ,  G06F13/38 ,  G06F13/42

    CPC classification number: G06F13/4022 ,  G06F13/387 ,  G06F13/4295 ,  G06F2213/0026

    Abstract: Described are embodiments of methods, apparatuses, and systems for PCIe tunneling across a multi-protocol I/O interconnect of a computer apparatus. A method for PCIe tunneling across the multi-protocol I/O interconnect may include establishing a first communication path between ports of a switching fabric of a multi-protocol I/O interconnect of a computer apparatus in response to a peripheral component interconnect express (PCIe) device being connected to the computer apparatus, and establishing a second communication path between the switching fabric and a PCIe controller. The method may further include routing, by the multi-protocol I/O interconnect, PCIe protocol packets of the PCIe device from the PCIe device to the PCIe controller over the first and second communication paths. Other embodiments may be described and claimed.

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