公开(公告)号：US10061707B2

公开(公告)日：2018-08-28

申请号：US15079922

申请日：2016-03-24

Applicant: Intel Corporation

Inventor： Shanthanand Kutuva Rabindranath ,  David J. Harriman ,  Prashant Sethi ,  Vijayalakshmi Kothandan

IPC: G06F13/20 ,  G06F12/10 ,  G06F13/42

CPC classification number: G06F12/10 ,  G06F12/1081 ,  G06F12/109 ,  G06F13/404 ,  G06F13/4282 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2213/0026

Abstract: A first device is determined as connected to a first one of a plurality of ports of a root complex. Addresses are assigned corresponding to a first hierarchy of devices including the first device. A second device is determined as connected through a mapping portal bridge at a second one of the ports of the root complex, the second device included in another second hierarchy of devices. A mapping table is generated that corresponds to the mapping portal bridge. The mapping table defines a translation between addressing used in a first view of a configuration address space of the system and addressing used in a second view of the configuration address space. The first view includes a view of the root complex and the second view includes a view corresponding to the second hierarchy of devices, the first hierarchy of devices being addressed according to the first view.

公开(公告)号：US20170185525A1

公开(公告)日：2017-06-29

申请号：US15079922

申请日：2016-03-24

Applicant: Intel Corporation

Inventor： Shanthanand Kutuva Rabindranath ,  David J. Harriman ,  Prashant Sethi ,  Vijayalakshmi Kothandan

IPC: G06F12/10 ,  G06F13/42

CPC classification number: G06F12/10 ,  G06F12/1081 ,  G06F12/109 ,  G06F13/404 ,  G06F13/4282 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2213/0026

Abstract: A first device is determined as connected to a first one of a plurality of ports of a root complex. Addresses are assigned corresponding to a first hierarchy of devices including the first device. A second device is determined as connected through a mapping portal bridge at a second one of the ports of the root complex, the second device included in another second hierarchy of devices. A mapping table is generated that corresponds to the mapping portal bridge. The mapping table defines a translation between addressing used in a first view of a configuration address space of the system and addressing used in a second view of the configuration address space. The first view includes a view of the root complex and the second view includes a view corresponding to the second hierarchy of devices, the first hierarchy of devices being addressed according to the first view.

公开(公告)号：US11768791B2

公开(公告)日：2023-09-26

申请号：US17734733

申请日：2022-05-02

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Reuven Rozic ,  Maxim Dan ,  Prashant Sethi ,  Robert E. Gough ,  Shanthanand Kutuva Rabindranath

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/404 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0024 ,  G06F2213/0026

Abstract: A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.

公开(公告)号：US20220334994A1

公开(公告)日：2022-10-20

申请号：US17734733

申请日：2022-05-02

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Reuven Rozic ,  Maxim Dan ,  Prashant Sethi ,  Robert E. Gough ,  Shanthanand Kutuva Rabindranath

IPC: G06F13/40 ,  G06F13/42

Abstract: A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.

公开(公告)号：US11321264B2

公开(公告)日：2022-05-03

申请号：US17136347

申请日：2020-12-29

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Reuven Rozic ,  Maxim Dan ,  Prashant Sethi ,  Robert E. Gough ,  Shanthanand Kutuva Rabindranath

IPC: G06F13/40 ,  G06F13/42

Abstract: A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.

公开(公告)号：US20210232522A1

公开(公告)日：2021-07-29

申请号：US17136347

申请日：2020-12-29

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Reuven Rozic ,  Maxim Dan ,  Prashant Sethi ,  Robert E. Gough ,  Shanthanand Kutuva Rabindranath

IPC: G06F13/40 ,  G06F13/42

Abstract: A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.

公开(公告)号：US20170255582A1

公开(公告)日：2017-09-07

申请号：US15281318

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Reuven Rozic ,  Maxim Dan ,  Prashant Sethi ,  Robert E. Gough ,  Shanthanand Kutuva Rabindranath

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/404 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0024 ,  G06F2213/0026

Abstract: A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.