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    ENHANCED NFV SWITCHING
    11.
    发明申请
    ENHANCED NFV SWITCHING 审中-公开

    公开(公告)号：US20180352038A1

    公开(公告)日：2018-12-06

    申请号：US15607832

    申请日：2017-05-30

    Applicant: Intel Corporation

    Inventor： Krishnamurthy Jambur Sathyanarayana ,  Niall Power ,  Christopher MacNamara ,  Mark D. Gray

    IPC: H04L29/08 ,  G06F9/455 ,  G06F9/50

    Abstract: A computing apparatus, including: a hardware platform; and a virtual switch (vSwitch) to operate on the hardware platform, the vSwitch including a virtual ingress interface, an inline virtual egress interface to communicatively couple to an inline data path, a diverted virtual egress interface to communicatively couple to a diverted data path, a diversion logic block, and logic to: communicatively couple to a local virtual machine (VM) via the diverted data path, the VM to provide an edge computing function; communicatively couple to a downstream data center via the inline data path; receive an incoming packet via the virtual ingress interface; determine that the incoming packet belongs to a class of packets for diversion processing; provide the incoming packet to the diversion logic block, wherein the diversion logic block is to determine that the packet is an edge computing flow to be diverted to the edge computing function via the diverted data path; and direct the incoming packet to the local VM via the diverted virtual egress interface.

    Technologies for cache side channel attack detection and mitigation
    13.
    发明授权
    Technologies for cache side channel attack detection and mitigation 有权

    公开(公告)号：US10860714B2

    公开(公告)日：2020-12-08

    申请号：US16022976

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： John J. Browne ,  Marcel Cornu ,  Timothy Verrall ,  Tomasz Kantecki ,  Niall Power ,  Weigang Li ,  Eoin Walsh ,  Maryam Tahhan

    IPC: G06F21/55 ,  G06F21/56

    Abstract: Technologies for cache side channel attack detection and mitigation include an analytics server and one or more monitored computing devices. The analytics server polls each computing device for analytics counter data. The computing device generates the analytics counter data using a resource manager of a processor of the computing device. The analytics counter data may include last-level cache data or memory bandwidth data. The analytics server identifies suspicious core activity based on the analytics counter data and, if identified, deploys a detection process to the computing device. The computing device executes the detection process to identify suspicious application activity. If identified, the computing device may perform one or more corrective actions. Corrective actions include limiting resource usage by a suspicious process using the resource manager of the processor. The resource manager may limit cache occupancy or memory bandwidth used by the suspicious process. Other embodiments are described and claimed.

    TECHNOLOGIES FOR PROVIDING EFFICIENT DETECTION OF IDLE POLL LOOPS
    14.
    发明申请
    TECHNOLOGIES FOR PROVIDING EFFICIENT DETECTION OF IDLE POLL LOOPS 审中-公开

    公开(公告)号：US20190041957A1

    公开(公告)日：2019-02-07

    申请号：US15951391

    申请日：2018-04-12

    Applicant: Intel Corporation

    Inventor： David Hunt ,  Niall Power ,  Kevin Devey ,  Changzheng Wei ,  Bruce Richardson ,  Eliezer Tamir ,  Andrew Cunningham ,  Chris MacNamara ,  Nemanja Marjanovic ,  Rory Sexton ,  John Browne

    IPC: G06F1/32

    Abstract: Technologies for providing efficient detection of idle poll loops include a compute device. The compute device has a compute engine that includes a plurality of cores and a memory. The compute engine is to determine a ratio of unsuccessful operations to successful operations over a predefined time period of a core of the plurality cores that is assigned to continually poll, within the predefined time period, a memory address for a change in status and determine whether the determined ratio satisfies a reference ratio of unsuccessful operations to successful operations. The reference ratio is indicative of a change in the operation of the assigned core. The compute engine is further to selectively increase or decrease a power usage of the assigned core as a function of whether the determined ratio satisfies the reference ratio. Other embodiments are also described and claimed.

    MEMORY RING-BASED JOB DISTRIBUTION FOR PROCESSOR CORES AND CO-PROCESSORS
    15.
    发明申请
    MEMORY RING-BASED JOB DISTRIBUTION FOR PROCESSOR CORES AND CO-PROCESSORS 审中-公开

    公开(公告)号：US20180285154A1

    公开(公告)日：2018-10-04

    申请号：US15473885

    申请日：2017-03-30

    Applicant: Intel Corporation

    Inventor： John J. Browne ,  Chris MacNamara ,  Tomasz Kantecki ,  Stephen Doyle ,  Sean Harte ,  Niall Power

    IPC: G06F9/48 ,  G06F9/50

    Abstract: An apparatus includes a processor, a co-processor and a memory ring. The memory ring includes a plurality of slots that are associated with a plurality of jobs. The processor is to apply a set of rules and based on the application of the set of rules, selectively access a first slot of the plurality of slots to read first data stored in the first slot representing a first job of the plurality of jobs and process the first job based on the first data. The co-processor is to apply the set of rules and based on the application of the set of rules, access a second slot of the plurality of slots other than the first slot to read second data representing a second job of the plurality of jobs and process the second job based on the second data.

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