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    MULTIPLE DEVICE PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) CARD
    2.
    发明申请
    MULTIPLE DEVICE PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) CARD 审中-公开

    公开(公告)号：US20190034372A1

    公开(公告)日：2019-01-31

    申请号：US15843201

    申请日：2017-12-15

    Applicant: Intel Corporation

    Inventor： Dirk Blevins ,  Kevin Devey ,  Todd Cameron Langley

    IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42

    Abstract: Techniques are provided for multiple device Peripheral Component Interface Express (PCIe) card having a single slot connector and each device interfaces with the single slot connector using distinct, unshared, data lane terminals of the single slot connector. In an example, a PCIe card can include a first device mounted to a circuit board and a second device mounted to the circuit board. The first device can be connected to a first plurality of data lane terminals of a single slot connector of the circuit board. The second device can be connected to a second plurality of data lane terminals of the single slot connector. The first plurality of data lane terminals can be distinct from the second plurality of data lane terminals.

    TECHNOLOGIES FOR PROVIDING EFFICIENT DETECTION OF IDLE POLL LOOPS
    4.
    发明申请
    TECHNOLOGIES FOR PROVIDING EFFICIENT DETECTION OF IDLE POLL LOOPS 审中-公开

    公开(公告)号：US20190041957A1

    公开(公告)日：2019-02-07

    申请号：US15951391

    申请日：2018-04-12

    Applicant: Intel Corporation

    Inventor： David Hunt ,  Niall Power ,  Kevin Devey ,  Changzheng Wei ,  Bruce Richardson ,  Eliezer Tamir ,  Andrew Cunningham ,  Chris MacNamara ,  Nemanja Marjanovic ,  Rory Sexton ,  John Browne

    IPC: G06F1/32

    Abstract: Technologies for providing efficient detection of idle poll loops include a compute device. The compute device has a compute engine that includes a plurality of cores and a memory. The compute engine is to determine a ratio of unsuccessful operations to successful operations over a predefined time period of a core of the plurality cores that is assigned to continually poll, within the predefined time period, a memory address for a change in status and determine whether the determined ratio satisfies a reference ratio of unsuccessful operations to successful operations. The reference ratio is indicative of a change in the operation of the assigned core. The compute engine is further to selectively increase or decrease a power usage of the assigned core as a function of whether the determined ratio satisfies the reference ratio. Other embodiments are also described and claimed.

    NETWORK FUNCTION VIRTUALIZATION ARCHITECTURE WITH DEVICE ISOLATION
    6.
    发明申请
    NETWORK FUNCTION VIRTUALIZATION ARCHITECTURE WITH DEVICE ISOLATION 审中-公开

    公开(公告)号：US20190042506A1

    公开(公告)日：2019-02-07

    申请号：US16027776

    申请日：2018-07-05

    Applicant: Intel Corporation

    Inventor： Kevin Devey ,  John Browne ,  Chris Macnamara ,  Eoin Walsh ,  Bruce Richardson ,  Andrew Cunningham ,  Niall Power ,  David Hunt ,  Changzheng Wei ,  Eliezer Tamir

    IPC: G06F13/38 ,  G06F1/32 ,  G06F9/455

    Abstract: A network system includes a central processing unit and a peripheral device in electrical communication with the central processing unit. The peripheral device has at least one power input and a data input. The network system also includes an out of band controller in electrical communication with the central processing unit, the peripheral device, and an external management interface. Responsive to an identified threat, the out of band controller is configured to disable the at least one power input and the data input to the peripheral device, where the disablement indicates to the central processing unit that a hot plug event has occurred with respect to the peripheral device. The out of band controller is also configured to enable auxiliary power to the peripheral device such that the out of band controller remains in communication with the peripheral device during remediation of the identified threat.

    TECHNOLOGIES FOR DEMOTING CACHE LINES TO SHARED CACHE
    7.
    发明申请
    TECHNOLOGIES FOR DEMOTING CACHE LINES TO SHARED CACHE 审中-公开

    公开(公告)号：US20190042419A1

    公开(公告)日：2019-02-07

    申请号：US16024773

    申请日：2018-06-30

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Bruce Richardson ,  Niall Power ,  Andrew Cunningham ,  David Hunt ,  Kevin Devey ,  Changzheng Wei

    IPC: G06F12/084 ,  G06F12/1072

    Abstract: Technologies for demoting cache lines to a shared cache include a compute device with at least one processor having multiple cores, a cache memory with a core-local cache and a shared cache, and a cache line demote device. A processor core of a processor of the compute device is configured to retrieve at least a portion of data of a received network packet and move the data into one or more core-local cache lines of the core-local cache. The processor core is further configured to perform a processing operation on the data and transmit a cache line demotion command to the cache line demote device subsequent to having completed the processing operation. The cache line demote device is configured to perform a cache line demotion operation to demote the data from the core-local cache lines to shared cache lines of the shared cache. Other embodiments are described herein.

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