公开(公告)号：US20190042310A1

公开(公告)日：2019-02-07

申请号：US15951650

申请日：2018-04-12

Applicant: Intel Corporation

Inventor： John Browne ,  Chris MacNamara ,  Tomasz Kantecki ,  Peter McCarthy ,  Ma Liang ,  Mairtin O'Loingsigh ,  Rory Sexton ,  John Griffin ,  Nemanja Marjanovic ,  David Hunt

IPC: G06F9/48 ,  G06F1/32 ,  H04L12/851

Abstract: Technologies for power-aware scheduling include a computing device that receives network packets. The computing device classifies the network packets by priority level and then assigns each network packet to a performance group bin. The packets are assigned based on priority level and other performance criteria. The computing device schedules the network packets assigned to each performance group for processing by a processing engine such as a processor core. Network packets assigned to performance groups having a high priority level are scheduled for processing by processing engines with a high performance level. The computing device may select performance levels for processing engines based on processing workload of the network packets. The computing device may control the performance level of the processing engines, for example by controlling the frequency of processor cores. The processing workload may include packet encryption. Other embodiments are described and claimed.

公开(公告)号：US11847008B2

公开(公告)日：2023-12-19

申请号：US15951391

申请日：2018-04-12

Applicant: Intel Corporation

Inventor： David Hunt ,  Niall Power ,  Kevin Devey ,  Changzheng Wei ,  Bruce Richardson ,  Eliezer Tamir ,  Andrew Cunningham ,  Chris MacNamara ,  Nemanja Marjanovic ,  Rory Sexton ,  John Browne

IPC: G06F1/00 ,  G06F1/3228 ,  G06F1/3296 ,  G06F15/00 ,  G06F1/324

CPC classification number: G06F1/3228 ,  G06F1/324 ,  G06F1/3296 ,  G06F15/00

Abstract: Technologies for providing efficient detection of idle poll loops include a compute device. The compute device has a compute engine that includes a plurality of cores and a memory. The compute engine is to determine a ratio of unsuccessful operations to successful operations over a predefined time period of a core of the plurality cores that is assigned to continually poll, within the predefined time period, a memory address for a change in status and determine whether the determined ratio satisfies a reference ratio of unsuccessful operations to successful operations. The reference ratio is indicative of a change in the operation of the assigned core. The compute engine is further to selectively increase or decrease a power usage of the assigned core as a function of whether the determined ratio satisfies the reference ratio. Other embodiments are also described and claimed.

公开(公告)号：US20180335824A1

公开(公告)日：2018-11-22

申请号：US15601296

申请日：2017-05-22

Applicant: Intel Corporation

Inventor： Christopher MacNamara ,  John J. Browne ,  William J. Bowhill ,  Christopher Nolan ,  Nemanja Marjanovic ,  Rory Sexton ,  Padraic Agnew ,  Colin Hanily

IPC: G06F1/32 ,  H04L12/26 ,  G06F1/26

Abstract: In an example, there is disclosed a demand scaling engine, including: a processor interface to communicatively couple to a processor; a network controller interface to communicatively couple to a network controller and to receive network demand data; a scaleup criterion; a current processor frequency scale datum; and logic, provided at least partly in hardware, to: receive the network demand data; compare the network demand data to the scaleup criterion; determine that the network demand data exceeds the scaleup criterion; and instruct the processor via the processor interface to scaleup processor frequency.

公开(公告)号：US11630693B2

公开(公告)日：2023-04-18

申请号：US15951650

申请日：2018-04-12

Applicant: Intel Corporation

Inventor： John Browne ,  Chris MacNamara ,  Tomasz Kantecki ,  Peter McCarthy ,  Liang Ma ,  Mairtin O'Loingsigh ,  Rory Sexton ,  John Griffin ,  Nemanja Marjanovic ,  David Hunt

IPC: G06F9/46 ,  G06F9/48 ,  H04L47/24 ,  G06F1/329 ,  H04L9/40 ,  H04L47/6275 ,  G06F1/3209 ,  G06F1/3296 ,  G06F1/3234 ,  H04L47/625 ,  G06F9/50 ,  G06F21/60

Abstract: Technologies for power-aware scheduling include a computing device that receives network packets. The computing device classifies the network packets by priority level and then assigns each network packet to a performance group bin. The packets are assigned based on priority level and other performance criteria. The computing device schedules the network packets assigned to each performance group for processing by a processing engine such as a processor core. Network packets assigned to performance groups having a high priority level are scheduled for processing by processing engines with a high performance level. The computing device may select performance levels for processing engines based on processing workload of the network packets. The computing device may control the performance level of the processing engines, for example by controlling the frequency of processor cores. The processing workload may include packet encryption. Other embodiments are described and claimed.

公开(公告)号：US11301020B2

公开(公告)日：2022-04-12

申请号：US15601296

申请日：2017-05-22

Applicant: Intel Corporation

Inventor： Christopher MacNamara ,  John J. Browne ,  William J. Bowhill ,  Christopher Nolan ,  Nemanja Marjanovic ,  Rory Sexton ,  Padraic Agnew ,  Colin Hanily

IPC: G06F1/32 ,  G06F1/3209 ,  H04L41/0893 ,  H04L43/16 ,  H04L43/08 ,  G06F1/26 ,  G06F1/324 ,  H04L43/0876

Abstract: In an example, there is disclosed a demand scaling engine, including: a processor interface to communicatively couple to a processor; a network controller interface to communicatively couple to a network controller and to receive network demand data; a scaleup criterion; a current processor frequency scale datum; and logic, provided at least partly in hardware, to: receive the network demand data; compare the network demand data to the scaleup criterion; determine that the network demand data exceeds the scaleup criterion; and instruct the processor via the processor interface to scaleup processor frequency.

公开(公告)号：US20190041957A1

公开(公告)日：2019-02-07

申请号：US15951391

申请日：2018-04-12

Applicant: Intel Corporation

Inventor： David Hunt ,  Niall Power ,  Kevin Devey ,  Changzheng Wei ,  Bruce Richardson ,  Eliezer Tamir ,  Andrew Cunningham ,  Chris MacNamara ,  Nemanja Marjanovic ,  Rory Sexton ,  John Browne

IPC: G06F1/32

Abstract: Technologies for providing efficient detection of idle poll loops include a compute device. The compute device has a compute engine that includes a plurality of cores and a memory. The compute engine is to determine a ratio of unsuccessful operations to successful operations over a predefined time period of a core of the plurality cores that is assigned to continually poll, within the predefined time period, a memory address for a change in status and determine whether the determined ratio satisfies a reference ratio of unsuccessful operations to successful operations. The reference ratio is indicative of a change in the operation of the assigned core. The compute engine is further to selectively increase or decrease a power usage of the assigned core as a function of whether the determined ratio satisfies the reference ratio. Other embodiments are also described and claimed.