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    REORDERING OF DATA FOR PARALLEL PROCESSING
    2.
    发明申请
    REORDERING OF DATA FOR PARALLEL PROCESSING 审中-公开

    公开(公告)号：US20190097951A1

    公开(公告)日：2019-03-28

    申请号：US15719081

    申请日：2017-09-28

    Applicant: Intel Corporation

    Inventor： Tomasz Kantecki ,  Niall Power ,  John J. Browne ,  Christopher MacNamara ,  Stephen Doyle

    IPC: H04L12/861 ,  H04L12/883

    Abstract: A network interface device, including: an ingress interface; a host platform interface to communicatively couple to a host platform; and a packet preprocessor including logic to: receive via the ingress interface a data sequence including a plurality of discrete data units; identify the data sequence as data for a parallel processing operation; reorder the discrete data units into a reordered data frame, the reordered data frame configured to order the discrete data units for consumption by the parallel operation; and send the reordered data to the host platform via the host platform interface.

    TECHNOLOGIES FOR CACHE SIDE CHANNEL ATTACK DETECTION AND MITIGATION
    3.
    发明申请
    TECHNOLOGIES FOR CACHE SIDE CHANNEL ATTACK DETECTION AND MITIGATION 审中-公开

    公开(公告)号：US20190042739A1

    公开(公告)日：2019-02-07

    申请号：US16022976

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： John J. Browne ,  Marcel Cornu ,  Timothy Verrall ,  Tomasz Kantecki ,  Niall Power ,  Weigang Li ,  Eoin Walsh ,  Maryam Tahhan

    IPC: G06F21/55 ,  G06F21/56

    Abstract: Technologies for cache side channel attack detection and mitigation include an analytics server and one or more monitored computing devices. The analytics server polls each computing device for analytics counter data. The computing device generates the analytics counter data using a resource manager of a processor of the computing device. The analytics counter data may include last-level cache data or memory bandwidth data. The analytics server identifies suspicious core activity based on the analytics counter data and, if identified, deploys a detection process to the computing device. The computing device executes the detection process to identify suspicious application activity. If identified, the computing device may perform one or more corrective actions. Corrective actions include limiting resource usage by a suspicious process using the resource manager of the processor. The resource manager may limit cache occupancy or memory bandwidth used by the suspicious process. Other embodiments are described and claimed.

    Reordering of data for parallel processing
    6.
    发明授权
    Reordering of data for parallel processing 有权

    公开(公告)号：US11050682B2

    公开(公告)日：2021-06-29

    申请号：US15719081

    申请日：2017-09-28

    Applicant: Intel Corporation

    Inventor： Tomasz Kantecki ,  Niall Power ,  John J. Browne ,  Christopher MacNamara ,  Stephen Doyle

    IPC: H04L12/861 ,  H04L12/883 ,  H04L12/801 ,  H04L12/935

    Abstract: A network interface device, including: an ingress interface; a host platform interface to communicatively couple to a host platform; and a packet preprocessor including logic to: receive via the ingress interface a data sequence including a plurality of discrete data units; identify the data sequence as data for a parallel processing operation; reorder the discrete data units into a reordered data frame, the reordered data frame configured to order the discrete data units for consumption by the parallel operation; and send the reordered data to the host platform via the host platform interface.

    Technologies for demoting cache lines to shared cache
    7.
    发明授权
    Technologies for demoting cache lines to shared cache 有权

    公开(公告)号：US10657056B2

    公开(公告)日：2020-05-19

    申请号：US16024773

    申请日：2018-06-30

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Bruce Richardson ,  Niall Power ,  Andrew Cunningham ,  David Hunt ,  Kevin Devey ,  Changzheng Wei

    IPC: G06F12/084 ,  G06F12/1072 ,  H04L12/933 ,  G06F12/128 ,  G06F13/28

    Abstract: Technologies for demoting cache lines to a shared cache include a compute device with at least one processor having multiple cores, a cache memory with a core-local cache and a shared cache, and a cache line demote device. A processor core of a processor of the compute device is configured to retrieve at least a portion of data of a received network packet and move the data into one or more core-local cache lines of the core-local cache. The processor core is further configured to perform a processing operation on the data and transmit a cache line demotion command to the cache line demote device subsequent to having completed the processing operation. The cache line demote device is configured to perform a cache line demotion operation to demote the data from the core-local cache lines to shared cache lines of the shared cache. Other embodiments are described herein.

    NETWORK FUNCTION VIRTUALIZATION ARCHITECTURE WITH DEVICE ISOLATION
    9.
    发明申请
    NETWORK FUNCTION VIRTUALIZATION ARCHITECTURE WITH DEVICE ISOLATION 审中-公开

    公开(公告)号：US20190042506A1

    公开(公告)日：2019-02-07

    申请号：US16027776

    申请日：2018-07-05

    Applicant: Intel Corporation

    Inventor： Kevin Devey ,  John Browne ,  Chris Macnamara ,  Eoin Walsh ,  Bruce Richardson ,  Andrew Cunningham ,  Niall Power ,  David Hunt ,  Changzheng Wei ,  Eliezer Tamir

    IPC: G06F13/38 ,  G06F1/32 ,  G06F9/455

    Abstract: A network system includes a central processing unit and a peripheral device in electrical communication with the central processing unit. The peripheral device has at least one power input and a data input. The network system also includes an out of band controller in electrical communication with the central processing unit, the peripheral device, and an external management interface. Responsive to an identified threat, the out of band controller is configured to disable the at least one power input and the data input to the peripheral device, where the disablement indicates to the central processing unit that a hot plug event has occurred with respect to the peripheral device. The out of band controller is also configured to enable auxiliary power to the peripheral device such that the out of band controller remains in communication with the peripheral device during remediation of the identified threat.

    TECHNOLOGIES FOR DEMOTING CACHE LINES TO SHARED CACHE
    10.
    发明申请
    TECHNOLOGIES FOR DEMOTING CACHE LINES TO SHARED CACHE 审中-公开

    公开(公告)号：US20190042419A1

    公开(公告)日：2019-02-07

    申请号：US16024773

    申请日：2018-06-30

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Bruce Richardson ,  Niall Power ,  Andrew Cunningham ,  David Hunt ,  Kevin Devey ,  Changzheng Wei

    IPC: G06F12/084 ,  G06F12/1072

    Abstract: Technologies for demoting cache lines to a shared cache include a compute device with at least one processor having multiple cores, a cache memory with a core-local cache and a shared cache, and a cache line demote device. A processor core of a processor of the compute device is configured to retrieve at least a portion of data of a received network packet and move the data into one or more core-local cache lines of the core-local cache. The processor core is further configured to perform a processing operation on the data and transmit a cache line demotion command to the cache line demote device subsequent to having completed the processing operation. The cache line demote device is configured to perform a cache line demotion operation to demote the data from the core-local cache lines to shared cache lines of the shared cache. Other embodiments are described herein.

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