公开(公告)号：US11972001B2

公开(公告)日：2024-04-30

申请号：US17743706

申请日：2022-05-13

Applicant: The Intel Corporation

Inventor： Ned M. Smith ,  Brinda Ganesh ,  Francesc Guim Bernat ,  Eoin Walsh ,  Evan Custodio

IPC: G06F21/60 ,  H04L9/08 ,  H04L9/40 ,  H04L41/5003 ,  H04L67/01

CPC classification number: G06F21/602 ,  H04L9/0827 ,  H04L41/5003 ,  H04L63/0428 ,  H04L63/045 ,  H04L63/0485 ,  H04L67/01

Abstract: Technologies for securely providing one or more remote accelerators hosted on edge resources to a client compute device includes a device that further includes an accelerator and one or more processors. The one or more processors are to determine whether to enable acceleration of an encrypted workload, receive, via an edge network, encrypted data from a client compute device, and transfer the encrypted data to the accelerator without exposing content of the encrypted data to the one or more processors. The accelerator is to receive, in response to a determination to enable the acceleration of the encrypted workload, an accelerator key from a secure server via a secured channel, and process, in response to a transfer of the encrypted data from the one or more processors, the encrypted data using the accelerator key.

公开(公告)号：US20210021484A1

公开(公告)日：2021-01-21

申请号：US17033557

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Kapil Sood ,  Timothy Verrall ,  Ned M. Smith ,  Tarun Viswanathan ,  Kshitij Doshi ,  Francesc Guim Bernat ,  John J. Browne ,  Katalin Bartfai-Walcott ,  Maryam Tahhan ,  Eoin Walsh ,  Damien Power

IPC: H04L12/24 ,  H04L29/06 ,  H04L12/26

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to schedule workloads based on secure edge to device telemetry by calculating a difference between a first telemetric data received from a first hardware device and an operating parameter and computing an adjustment for a second hardware device based on the difference between the first telemetric data and the operating parameter.

公开(公告)号：US20190042739A1

公开(公告)日：2019-02-07

申请号：US16022976

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： John J. Browne ,  Marcel Cornu ,  Timothy Verrall ,  Tomasz Kantecki ,  Niall Power ,  Weigang Li ,  Eoin Walsh ,  Maryam Tahhan

IPC: G06F21/55 ,  G06F21/56

Abstract: Technologies for cache side channel attack detection and mitigation include an analytics server and one or more monitored computing devices. The analytics server polls each computing device for analytics counter data. The computing device generates the analytics counter data using a resource manager of a processor of the computing device. The analytics counter data may include last-level cache data or memory bandwidth data. The analytics server identifies suspicious core activity based on the analytics counter data and, if identified, deploys a detection process to the computing device. The computing device executes the detection process to identify suspicious application activity. If identified, the computing device may perform one or more corrective actions. Corrective actions include limiting resource usage by a suspicious process using the resource manager of the processor. The resource manager may limit cache occupancy or memory bandwidth used by the suspicious process. Other embodiments are described and claimed.

公开(公告)号：US20190004922A1

公开(公告)日：2019-01-03

申请号：US15637706

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： John J. Browne ,  Tomasz Kantecki ,  Wojciech Andralojc ,  Timothy Verrall ,  Maryam Tahhan ,  Eoin Walsh ,  Damien Power ,  Chris Macnamara

IPC: G06F11/34 ,  G06F11/30

CPC classification number: G06F11/3495 ,  G06F11/0751 ,  G06F11/0793 ,  G06F11/3017 ,  G06F11/3409 ,  G06F11/348 ,  G06F2201/88 ,  G06N5/045 ,  G06N20/00

Abstract: A method for monitoring health of processes includes a compute device having a performance monitoring parameter manager and an analytics engine. The compute device accesses performance monitoring parameters associated with a monitored process of the compute device. The compute device samples one or more hardware counters associated with the monitored process and applies a performance monitor filter to the sampled one or more hardware counters to generate hardware counter values. The compute device performs a process fault check on the monitored process based on the hardware counter values and the performance monitoring parameters.

公开(公告)号：US20180357099A1

公开(公告)日：2018-12-13

申请号：US15617375

申请日：2017-06-08

Applicant: Intel Corporation

Inventor： John J. Browne ,  Tomasz Kantecki ,  Eoin Walsh ,  Maryam Tahhan ,  Timothy Verrall ,  Tarun Viswanathan ,  Rory Browne

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/455

CPC classification number: G06F9/5005 ,  G06F9/45504 ,  G06F9/4881

Abstract: Particular embodiments described herein provide for a network element that can be configured to determine a pre-execution performance test, where the pre-execution performance test is at least partially based on requirements for a process to be executed, cause the pre-execution performance test to be executed on a platform before the process is executed on the platform, where the platform is a dynamically allocated group of resources, analyze results of the pre-execution performance test, and cause the process to be executed on the platform if the results of the pre-execution performance test satisfy a condition. In an example, the process is a virtual network function.

公开(公告)号：US20230035468A1

公开(公告)日：2023-02-02

申请号：US17743706

申请日：2022-05-13

Applicant: The Intel Corporation

Inventor： Ned M. Smith ,  Brinda Ganesh ,  Francesc Guim Bernat ,  Eoin Walsh ,  Evan Custodio

IPC: G06F21/60 ,  H04L9/40 ,  H04L41/5003 ,  H04L9/08

Abstract: Technologies for securely providing one or more remote accelerators hosted on edge resources to a client compute device includes a device that further includes an accelerator and one or more processors. The one or more processors are to determine whether to enable acceleration of an encrypted workload, receive, via an edge network, encrypted data from a client compute device, and transfer the encrypted data to the accelerator without exposing content of the encrypted data to the one or more processors. The accelerator is to receive, in response to a determination to enable the acceleration of the encrypted workload, an accelerator key from a secure server via a secured channel, and process, in response to a transfer of the encrypted data from the one or more processors, the encrypted data using the accelerator key.

公开(公告)号：US20210075732A1

公开(公告)日：2021-03-11

申请号：US16953210

申请日：2020-11-19

Applicant: Intel Corporation

Inventor： Jasvinder Singh ,  Thomas Long ,  Eoin Walsh ,  John J. Browne

IPC: H04L12/851 ,  H04L12/865 ,  H04L12/869 ,  H04L12/863 ,  H04L12/927

Abstract: In one embodiment, a system comprises an interface to receive a plurality of packets; and a plurality of processor units to execute a plurality of transmission sub-interfaces, each transmission sub-interface to perform hierarchical quality of service (HQoS) scheduling on a distinct subset of the plurality of packets, wherein each transmission sub-interface is to schedule its subset of the plurality of packets for transmission by a network interface controller by assigning the packets of the subset to a plurality of transmission queues that each correspond to a distinct traffic class.

公开(公告)号：US20190394081A1

公开(公告)日：2019-12-26

申请号：US16015247

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Maryam Tahhan ,  John Joseph Browne ,  Eoin Walsh ,  Timothy Verrall ,  Rory Browne ,  Emma Louise Foley ,  Shobhi Jain ,  Peter Mangan

IPC: H04L12/24 ,  H04L12/26

Abstract: There is disclosed in one example a computing apparatus, including: a local platform including a hardware platform; a management interface to communicatively couple the local platform to a management controller; a virtualization infrastructure to operate on the hardware platform and to provide a local virtualized function; and a resiliency controller to operate on the hardware platform, and configured to: receive a resiliency policy from the management controller via the management interface, the resiliency policy including information to handle a fault in the virtualized function; detect a fault in the local virtualized function; and effect a resiliency action responsive to detecting the fault.

公开(公告)号：US20190042314A1

公开(公告)日：2019-02-07

申请号：US15869909

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Timothy Verrall ,  John J. Browne ,  Tomasz Kantecki ,  Maryam Tahhan ,  Eoin Walsh ,  Andrew Duignan ,  Alan Carey ,  Wojciech Andralojc ,  Damien Power ,  Tarun Viswanathan

IPC: G06F9/50 ,  G06F9/48

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to partition a resource into a plurality of partitions and allocate a reserved portion and a corresponding burst portion in each of the plurality of partitions. Each of the allocated reserved portions and corresponding burst portions are reserved for a specific component or application, where any part of the allocated burst portion not being used by the specific component or application can be used by other components and/or applications.

公开(公告)号：US10754783B2

公开(公告)日：2020-08-25

申请号：US16024611

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Tomasz Kantecki ,  John Browne ,  Chris Macnamara ,  Timothy Verrall ,  Marcel Cornu ,  Eoin Walsh ,  Andrew J. Herdrich

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/00 ,  G06F12/0891 ,  G06F9/50 ,  G06F9/455

Abstract: Examples include techniques to manage cache resource allocations associated with one or more cache class of service (CLOS) assignments for a processor cache. Examples include flushing portions of an allocated cache resource responsive to reassignments of CLOS.