公开(公告)号：US20230290728A1

公开(公告)日：2023-09-14

申请号：US18199735

申请日：2023-05-19

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Bharat P. PENMECHA ,  Rajasekaran SWAMINATHAN ,  Ram VISWANATH

IPC: H01L23/528 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/5283 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5384 ,  H01L24/17 ,  H01L24/23 ,  H01L25/0655 ,  H01L25/18

Abstract: Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

公开(公告)号：US20200273784A1

公开(公告)日：2020-08-27

申请号：US16646529

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Robert L. SANKMAN ,  Robert NICKERSON ,  Mitul MODI ,  Sanka GANESAN ,  Rajasekaran SWAMINATHAN ,  Omkar KARHADE ,  Shawna M. LIFF ,  Amruthavalli ALUR ,  Sri Chaitra J. CHAVALI

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

公开(公告)号：US20160343680A1

公开(公告)日：2016-11-24

申请号：US15225757

申请日：2016-08-01

Applicant: INTEL CORPORATION

Inventor： Rajasekaran SWAMINATHAN ,  Leonel R. ARANA ,  Yoshihiro TOMITA ,  Yosuke KANAOKA

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L24/16 ,  H01L21/4853 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11849 ,  H01L2224/16012 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/181 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2203/043 ,  H05K2203/083 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.