公开(公告)号：US20160247763A1

公开(公告)日：2016-08-25

申请号：US15147411

申请日：2016-05-05

申请人： Intel Corporation

发明人： Chia-Pin Chiu ,  Kinya Ichikawa ,  Robert L. Sankman

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/18 ,  H01L23/31

CPC分类号： H01L23/5381 ,  H01L21/486 ,  H01L21/4867 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L24/23 ,  H01L24/24 ,  H01L24/25 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/215 ,  H01L2224/24225 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15747 ,  H05K1/113 ,  H05K3/3436 ,  H05K3/4664 ,  H05K3/4694 ,  H05K2203/013 ,  H01L2924/00014 ,  H01L2924/00

摘要： Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a technique can include creating a multidie substrate, printing an interconnect bridge on the multidie substrate, electrically coupling a first die to a second die by coupling the first and second dies through the interconnect bridge.

摘要翻译： 这里通常讨论的是包括密集互连桥和其制造技术的系统和装置。 根据一个示例，一种技术可以包括创建多芯基板，在多芯基板上印刷互连桥，通过将第一和第二裸片耦合通过互连桥将第一裸片电耦合到第二裸片。

公开(公告)号：US09936575B2

公开(公告)日：2018-04-03

申请号：US15160190

申请日：2016-05-20

申请人： Murata Manufacturing Co., Ltd.

发明人： Yoshihito Otsubo

IPC分类号： H05K1/00 ,  H05K1/02 ,  H01L23/00 ,  H05K1/11 ,  H05K3/46 ,  H05K1/03 ,  H05K1/09 ,  H05K3/34

CPC分类号： H05K1/0298 ,  H01L24/23 ,  H05K1/0271 ,  H05K1/028 ,  H05K1/0313 ,  H05K1/09 ,  H05K1/115 ,  H05K1/116 ,  H05K3/3436 ,  H05K3/4632 ,  H05K2201/0129

摘要： A resin multilayer substrate includes a first resin layer, a conductive pattern that covers a portion of the first resin layer, a conductive via connected to the conductive pattern, and a second resin layer that is overlaid on the first resin layer. The second resin layer includes an opening through which the conductive pattern is partially exposed. As seen in plan view, the opening includes an inner peripheral edge including a first portion that is spaced from the conductive via by a first distance, and a second portion that is spaced from the conductive via by a second distance. The conductive pattern has a length that starts from the inner peripheral edge of the opening to outside and extends under the second resin layer. The length of the conductive pattern at the second portion is greater than the length of the conductive pattern at the first portion.

公开(公告)号：US20160270221A1

公开(公告)日：2016-09-15

申请号：US15160190

申请日：2016-05-20

申请人： Murata Manufacturing Co., Ltd.

发明人： Yoshihito OTSUBO

IPC分类号： H05K1/02 ,  H05K3/46 ,  H05K1/11 ,  H05K1/03 ,  H05K1/09

CPC分类号： H05K1/0298 ,  H01L24/23 ,  H05K1/0271 ,  H05K1/028 ,  H05K1/0313 ,  H05K1/09 ,  H05K1/115 ,  H05K1/116 ,  H05K3/3436 ,  H05K3/4632 ,  H05K2201/0129

摘要： A resin multilayer substrate includes a first resin layer, a conductive pattern that covers a portion of the first resin layer, a conductive via connected to the conductive pattern, and a second resin layer that is overlaid on the first resin layer. The second resin layer includes an opening through which the conductive pattern is partially exposed. As seen in plan view, the opening includes an inner peripheral edge including a first portion that is spaced from the conductive via by a first distance, and a second portion that is spaced from the conductive via by a second distance. The conductive pattern has a length that starts from the inner peripheral edge of the opening to outside and extends under the second resin layer. The length of the conductive pattern at the second portion is greater than the length of the conductive pattern at the first portion.

摘要翻译： 树脂多层基板包括第一树脂层，覆盖第一树脂层的一部分的导电图案，连接到导电图案的导电通孔以及覆盖在第一树脂层上的第二树脂层。 第二树脂层包括导电图案部分露出的开口。 如在平面图中所看到的，开口包括内周缘，该内周边缘包括与导电通孔隔开第一距离的第一部分，以及与导电通路间隔第二距离的第二部分。 导电图案具有从开口的内周边缘开始到外部并在第二树脂层下方延伸的长度。 第二部分处的导电图案的长度大于第一部分处的导电图案的长度。

公开(公告)号：US09287205B2

公开(公告)日：2016-03-15

申请号：US14693995

申请日：2015-04-23

申请人： NANTONG FUJITSU MICROELECTRONICS CO., LTD.

发明人： Lei Shi ,  Yujuan Tao

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L21/50 ,  H05K1/03 ,  H05K1/11 ,  H05K1/18

CPC分类号： H01L23/49822 ,  H01L21/50 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/23 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/85005 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/0306 ,  H05K1/111 ,  H05K1/181 ,  H05K1/185 ,  H05K2201/0154 ,  H05K2201/0195 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/00012

摘要： A fan-out high-density packaging method includes providing a packaging substrate, forming a stripping film on the packaging substrate, and forming a first protection layer on the stripping film and pre-designed photolithography pattern openings on the first protection layer. The method also includes forming a metal redistribution layer on the surface of the first protection layer and in the photolithography pattern openings, forming a second protection layer on the first protection layer and partially exposing the metal redistribution layer, and forming at least one package layer on the second protection layer. Each of at least one package layer includes a straight mounting layer, a sealant layer, and a wiring layer formed in sequence, and the package layer connects the metal redistribution layer through the wiring layer. Further, the method includes forming at least one top-level package layer on top of the at least one package layer, removing the packaging substrate and the stripping film to expose the metal redistribution layer in the first protection layer, and planting metal solder balls on the exposed metal redistribution layer.

公开(公告)号：US09040347B2

公开(公告)日：2015-05-26

申请号：US13984889

申请日：2012-03-22

申请人： Yujuan Tao ,  Lei Shi

发明人： Yujuan Tao ,  Lei Shi

IPC分类号： H01L21/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/50

CPC分类号： H01L23/49822 ,  H01L21/50 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/23 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/85005 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/0306 ,  H05K1/111 ,  H05K1/181 ,  H05K1/185 ,  H05K2201/0154 ,  H05K2201/0195 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/00012

摘要： A fan-out high-density packaging method includes providing a packaging substrate, forming a stripping film on the packaging substrate, and forming a first protection layer on the stripping film and pre-designed photolithography pattern openings on the first protection layer. The method also includes forming a metal redistribution layer on the surface of the first protection layer and in the photolithography pattern openings, forming a second protection layer on the first protection layer and partially exposing the metal redistribution layer, and forming at least one package layer on the second protection layer. Each of at least one package layer includes a straight mounting layer, a sealant layer, and a wiring layer formed in sequence, and the package layer connects the metal redistribution layer through the wiring layer. Further, the method includes forming at least one top-level package layer on top of the at least one package layer, removing the packaging substrate and the stripping film to expose the metal redistribution layer in the first protection layer, and planting metal solder balls on the exposed metal redistribution layer.

摘要翻译： 扇出式高密度封装方法包括提供封装衬底，在封装衬底上形成剥离膜，以及在剥离膜上形成第一保护层和在第一保护层上形成预先设计的光刻图案孔。 该方法还包括在第一保护层的表面上和在光刻图案开口中形成金属再分配层，在第一保护层上形成第二保护层，并部分地暴露金属再分布层，并且形成至少一个封装层 第二保护层。 至少一个封装层中的每一个包括依次形成的直的安装层，密封剂层和布线层，并且封装层通过布线层连接金属再分配层。 此外，该方法包括在至少一个封装层的顶部上形成至少一个顶层封装层，去除封装衬底和剥离膜以暴露第一保护层中的金属再分配层，并将金属焊球放置在 暴露的金属再分配层。

公开(公告)号：US09741664B2

公开(公告)日：2017-08-22

申请号：US15147411

申请日：2016-05-05

申请人： Intel Corporation

发明人： Chia-Pin Chiu ,  Kinya Ichikawa ,  Robert L. Sankman

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L25/065 ,  H01L23/31 ,  H01L25/18 ,  H01L23/498 ,  H05K1/11 ,  H05K3/34 ,  H05K3/46

CPC分类号： H01L23/5381 ,  H01L21/486 ,  H01L21/4867 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L24/23 ,  H01L24/24 ,  H01L24/25 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/215 ,  H01L2224/24225 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15747 ,  H05K1/113 ,  H05K3/3436 ,  H05K3/4664 ,  H05K3/4694 ,  H05K2203/013 ,  H01L2924/00014 ,  H01L2924/00

摘要： Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a technique can include creating a multidie substrate, printing an interconnect bridge on the multidie substrate, electrically coupling a first die to a second die by coupling the first and second dies through the interconnect bridge.

公开(公告)号：US20150228568A1

公开(公告)日：2015-08-13

申请号：US14693995

申请日：2015-04-23

申请人： NANTONG FUJITSU MICROELECTRONICS CO., LTD.

发明人： LEI SHI ,  YUJUAN TAO

IPC分类号： H01L23/498 ,  H05K1/11 ,  H05K1/18 ,  H01L23/31 ,  H05K1/03

CPC分类号： H01L23/49822 ,  H01L21/50 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/23 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/85005 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/0306 ,  H05K1/111 ,  H05K1/181 ,  H05K1/185 ,  H05K2201/0154 ,  H05K2201/0195 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/00012

摘要： A fan-out high-density packaging method includes providing a packaging substrate, forming a stripping film on the packaging substrate, and forming a first protection layer on the stripping film and pre-designed photolithography pattern openings on the first protection layer. The method also includes forming a metal redistribution layer on the surface of the first protection layer and in the photolithography pattern openings, forming a second protection layer on the first protection layer and partially exposing the metal redistribution layer, and forming at least one package layer on the second protection layer. Each of at least one package layer includes a straight mounting layer, a sealant layer, and a wiring layer formed in sequence, and the package layer connects the metal redistribution layer through the wiring layer. Further, the method includes forming at least one top-level package layer on top of the at least one package layer, removing the packaging substrate and the stripping film to expose the metal redistribution layer in the first protection layer, and planting metal solder balls on the exposed metal redistribution layer.

摘要翻译： 扇出式高密度封装方法包括提供封装衬底，在封装衬底上形成剥离膜，以及在剥离膜上形成第一保护层，并在第一保护层上形成预先设计的光刻图案孔。 该方法还包括在第一保护层的表面上和在光刻图案开口中形成金属再分配层，在第一保护层上形成第二保护层，并部分地暴露金属再分布层，并且形成至少一个封装层 第二保护层。 至少一个封装层中的每一个包括依次形成的直的安装层，密封剂层和布线层，并且封装层通过布线层连接金属再分配层。 此外，该方法包括在至少一个封装层的顶部上形成至少一个顶层封装层，去除封装衬底和剥离膜以暴露第一保护层中的金属再分配层，并将金属焊球放置在 暴露的金属再分配层。

公开(公告)号：US08766440B2

公开(公告)日：2014-07-01

申请号：US13582128

申请日：2011-01-25

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Kentaro Mori ,  Yoshiki Nakashima ,  Daisuke Ohshima

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Kentaro Mori ,  Yoshiki Nakashima ,  Daisuke Ohshima

IPC分类号： H01L23/52

CPC分类号： H05K1/186 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/23 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2101 ,  H01L2224/221 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1461 ,  H05K3/4644 ,  H01L2924/00

摘要： A wiring board including a built-in semiconductor element includes the semiconductor element, a peripheral insulating layer covering an outer peripheral side surface of the semiconductor element, an upper surface-side wiring provided on an upper surface side of the wiring board, and a lower surface-side wiring provided on a lower surface side of the wiring board. The semiconductor element includes a first wiring structure layer including a first wiring and a first insulating layer alternately provided on a semiconductor substrate, and a second wiring structure layer including a second wiring and a second insulating layer alternately provided on the first wiring structure layer. The upper surface-side wiring includes a wiring electrically connected to the first wiring via the second wiring. The second wiring is thicker than the first wiring and thinner than the upper surface-side wiring. The second insulating layer is formed of a resin material and is thicker than the first insulating layer.

摘要翻译： 包括内置半导体元件的布线板包括半导体元件，覆盖半导体元件的外周侧表面的外围绝缘层，设置在布线基板的上表面侧的上表面侧布线，以及下部 设置在布线基板的下表面侧的表面侧配线。 半导体元件包括：第一布线结构层，包括交替设置在半导体基板上的第一布线和第一绝缘层;以及第二布线结构层，包括交替设置在第一布线结构层上的第二布线和第二绝缘层。 上表面侧布线包括经由第二布线电连接到第一布线的布线。 第二布线比第一布线厚，比上表面布线薄。 第二绝缘层由树脂材料形成，并且比第一绝缘层厚。

公开(公告)号：US20120319254A1

公开(公告)日：2012-12-20

申请号：US13582128

申请日：2011-01-25

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Kentaro Mori ,  Yoshiki Nakashima ,  Daisuke Ohshima

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Kentaro Mori ,  Yoshiki Nakashima ,  Daisuke Ohshima

IPC分类号： H01L23/48 ,  H01L23/552

CPC分类号： H05K1/186 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/23 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2101 ,  H01L2224/221 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1461 ,  H05K3/4644 ,  H01L2924/00

摘要： A wiring board including a built-in semiconductor element includes the semiconductor element, a peripheral insulating layer covering an outer peripheral side surface of the semiconductor element, an upper surface-side wiring provided on an upper surface side of the wiring board, and a lower surface-side wiring provided on a lower surface side of the wiring board. The semiconductor element includes a first wiring structure layer including a first wiring and a first insulating layer alternately provided on a semiconductor substrate, and a second wiring structure layer including a second wiring and a second insulating layer alternately provided on the first wiring structure layer. The upper surface-side wiring includes a wiring electrically connected to the first wiring via the second wiring. The second wiring is thicker than the first wiring and thinner than the upper surface-side wiring. The second insulating layer is formed of a resin material and is thicker than the first insulating layer.

摘要翻译： 包括内置半导体元件的布线板包括半导体元件，覆盖半导体元件的外周侧表面的外围绝缘层，设置在布线基板的上表面侧的上表面侧布线，以及下部 设置在布线基板的下表面侧的表面侧配线。 半导体元件包括：第一布线结构层，包括交替设置在半导体基板上的第一布线和第一绝缘层;以及第二布线结构层，包括交替设置在第一布线结构层上的第二布线和第二绝缘层。 上表面侧布线包括经由第二布线电连接到第一布线的布线。 第二布线比第一布线厚，比上表面布线薄。 第二绝缘层由树脂材料形成，并且比第一绝缘层厚。

公开(公告)号：US20190130152A1

公开(公告)日：2019-05-02

申请号：US15981311

申请日：2018-05-16

申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.

发明人： Byung Ho KIM ,  Da Hee KIM ,  Joon Sung KIM ,  Joo Young CHOI ,  Hee Sook PARK ,  Tae Wook KIM

IPC分类号： G06K9/00 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

CPC分类号： G06K9/0002 ,  G06K9/00053 ,  H01L21/56 ,  H01L23/053 ,  H01L23/055 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/09 ,  H01L24/14 ,  H01L24/20 ,  H01L24/23 ,  H01L24/24 ,  H01L24/49 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/18 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/0001 ,  H01L2224/45099

摘要： A fan-out semiconductor package includes: a core member including a support layer, a first wiring layer, a second wiring layer, and through-vias and having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant covering the core member and the semiconductor chip and filling at least portions of the through-hole; a connection member including an insulating layer disposed on the first wiring layer and the semiconductor chip, a redistribution layer disposed on the insulating layer, first vias electrically connecting the redistribution layer and the connection pads to each other, and second vias electrically connecting the redistribution layer and the first wiring layer to each other; and a passivation layer disposed on the insulating layer and covering the redistribution layer, wherein a thickness of the passivation layer is within half a distance from an inactive surface of the semiconductor chip to a lower surface of the encapsulant.