公开(公告)号：US20150194401A1

公开(公告)日：2015-07-09

申请号：US14658089

申请日：2015-03-13

Applicant: INTEL CORPORATION

Inventor： Rajasekaran SWAMINATHAN ,  Leonel R. ARANA ,  Yoshihiro TOMITA ,  Yosuke KANAOKA

IPC: H01L23/00 ,  H01L25/10

CPC classification number: H01L24/16 ,  H01L21/4853 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11849 ,  H01L2224/16012 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/181 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2203/043 ,  H05K2203/083 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.

Abstract translation: 描述形成微电子封装结构的方法。 这些方法可以包括在衬底上形成包含牺牲聚合物的焊膏，将焊膏固化在焊料的回流温度以下，以在导电焊盘上形成固体复合混合凸块，在固体复合混合凸块周围形成模塑料， 并且回流混合凸块，其中牺牲聚合物基本分解。

公开(公告)号：US20220285278A1

公开(公告)日：2022-09-08

申请号：US17752717

申请日：2022-05-24

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Hiroki TANAKA ,  Oscar OJEDA ,  Arnab ROY ,  Vahidreza PARICHEHREH ,  Leonel R. ARANA ,  Chung Kwang TAN ,  Robert A. MAY

IPC: H01L23/538 ,  H01L21/48

Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.

公开(公告)号：US20170032991A1

公开(公告)日：2017-02-02

申请号：US15295943

申请日：2016-10-17

Applicant: INTEL CORPORATION

Inventor： John C. JOHNSON ,  Sandeep B. SANE ,  Sandeep RAZDAN ,  Edward R. PRACK ,  Leonel R. ARANA ,  Peter A. DAVISON ,  Eric J. MORET ,  Lawrence M. PALANUK ,  Gregory A. STONE

IPC: H01L21/673 ,  H01L21/78 ,  H01L21/683 ,  H01L21/67 ,  H01L21/677

CPC classification number: H01L21/67333 ,  H01L21/67265 ,  H01L21/67309 ,  H01L21/67356 ,  H01L21/67363 ,  H01L21/67383 ,  H01L21/67769 ,  H01L21/67772 ,  H01L21/67778 ,  H01L21/68 ,  H01L21/6833 ,  H01L21/68764 ,  H01L21/68771 ,  H01L21/78 ,  H05K13/0084

Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.

Abstract translation: 一种方法包括识别晶片上的多个管芯的晶片位置，将多个管芯中的每个管芯的晶片位置存储在数据库中，将晶片切割成多个单个管芯，将每个单模管芯定位在管芯中 在托盘上的位置位置，并将模具位置存储在数据库中的每个单个模具的托盘上。 数据库包括包括与每个模具位置相关联的晶片位置的信息。 托盘被运送到处理工具，并且多个分割模具中的至少一个从托盘上的模具位置移除并在处理工具中进行处理。 在处理之前，单独模具位于托盘上的相同的限定位置处理被处理的单个模具。 描述和要求保护其他实施例。

公开(公告)号：US20160343680A1

公开(公告)日：2016-11-24

申请号：US15225757

申请日：2016-08-01

Applicant: INTEL CORPORATION

Inventor： Rajasekaran SWAMINATHAN ,  Leonel R. ARANA ,  Yoshihiro TOMITA ,  Yosuke KANAOKA

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L24/16 ,  H01L21/4853 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11849 ,  H01L2224/16012 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/181 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2203/043 ,  H05K2203/083 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.

公开(公告)号：US20160172222A1

公开(公告)日：2016-06-16

申请号：US15050387

申请日：2016-02-22

Applicant: INTEL CORPORATION

Inventor： John C. JOHNSON ,  Sandeep B. SANE ,  Sandeep RAZDAN ,  Edward R. PRACK ,  Leonel R. ARANA ,  Peter A. DAVISON ,  Eric J. MORET ,  Lawrence M. PALANUK ,  Gregory A. STONE

IPC: H01L21/673 ,  H01L21/683 ,  H01L21/78 ,  H01L21/67 ,  H01L21/677

CPC classification number: H01L21/67333 ,  H01L21/67265 ,  H01L21/67309 ,  H01L21/67356 ,  H01L21/67363 ,  H01L21/67383 ,  H01L21/67769 ,  H01L21/67772 ,  H01L21/67778 ,  H01L21/68 ,  H01L21/6833 ,  H01L21/68764 ,  H01L21/68771 ,  H01L21/78 ,  H05K13/0084

Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.