公开(公告)号：US11139241B2

公开(公告)日：2021-10-05

申请号：US16348105

申请日：2016-12-07

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Mauro J. Kobrinsky ,  Mark T. Bohr ,  Tahir Ghani ,  Rishabh Mehandru ,  Ranjith Kumar

IPC: H01L23/528 ,  H01L27/02 ,  H01L21/306 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/417 ,  H01L29/772 ,  H01L23/522 ,  G06F30/392 ,  G06F30/394

Abstract: Integrated circuit (IC) cell architectures including a crenellated interconnect trace layout. A crenellated trace layout may be employed where an IC cell includes transistor having a source/drain terminal interconnected through a back-side (3D) routing scheme that reduces front-side routing density for a given transistor footprint. In the crenellated layout, adjacent interconnect traces or tracks may have their ends staggered according to a crenellation phase for the cell. Crenellated tracks may intersect one cell boundary with adjacent tracks intersecting an opposite cell boundary. Track ends may be offset by at least the width of an underlying orthogonal interconnect trace. Crenellated track ends may be offset by the width of an underlying orthogonal interconnect trace and half a spacing between adjacent orthogonal interconnect traces.

公开(公告)号：US11068640B2

公开(公告)日：2021-07-20

申请号：US16649588

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Ranjith Kumar ,  Mark T. Bohr ,  Ruth A. Brain ,  Marni Nabors ,  Tai-Hsuan Wu ,  Sourav Chakravarty

IPC: G06F30/3953 ,  G06F113/18 ,  G06F115/08 ,  H01L23/50 ,  H01L23/522

Abstract: An integrated circuit structure includes a metal level comprising a plurality of interconnect lines along a first direction. A cell is on the metal level, wherein one or more of the plurality of interconnect lines that extend through the cell comprise a power shared track that is segmented inside the cell into one or more power segments and one or more signal segments so that both power and signals share a same track.