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    POST-QUANTUM SECURE REMOTE ATTESTATION FOR AUTONOMOUS SYSTEMS
    11.
    发明申请
    POST-QUANTUM SECURE REMOTE ATTESTATION FOR AUTONOMOUS SYSTEMS 有权

    公开(公告)号：US20210119799A1

    公开(公告)日：2021-04-22

    申请号：US17133558

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： SANTOSH GHOSH ,  Marcio Juliato ,  Manoj Sastry

    IPC: H04L9/32 ,  H04L9/08 ,  G06F8/71

    Abstract: A method comprises maintaining, for at least one remote device, a security footprint and a verified version of a software stack for the remote device, generating an attestation initiation token that includes a nonce to be used to generate an XMSS signature for attestation of the remote device, sending the attestation initiation token to the remote device, receiving, from the remote device, a modified message representative including a hash of a current version of a software stack for the remote device and an indicator of a version number of the current version of the software stack for the remote device, validating the hash, and in response to a determination that the hash is valid, generating an XMSS signature using the security footprint and the current version of a software stack for the remote device and a security footprint for the apparatus.

    SINGLE CLOCK CYCLE CRYPTOGRAPHIC ENGINE
    14.
    发明申请
    SINGLE CLOCK CYCLE CRYPTOGRAPHIC ENGINE 审中-公开

    公开(公告)号：US20170353298A1

    公开(公告)日：2017-12-07

    申请号：US15173492

    申请日：2016-06-03

    Applicant: Intel Corporation

    Inventor： SANTOSH GHOSH

    IPC: H04L9/06 ,  H04L9/14 ,  G06F21/60

    CPC classification number: H04L9/0631 ,  G06F21/602 ,  H04L9/14

    Abstract: One embodiment provides an apparatus. The apparatus includes a cryptographic engine to encrypt or decrypt a 64-bit input data block based, at least in part, on a 128-bit input key. The cryptographic engine includes an input stage; a first group of rounds; a middle stage; a second group of inverse rounds and an output stage. Each round includes a first substitution box (“sbox”) stage, a first matrix multiplication stage, a row permutation stage and a first plurality of mixers. Each inverse round includes a second plurality of mixers, an inverse row permutation stage, a second matrix multiplication stage and a second inverse sbox stage. Each sbox stage includes a plurality of sbox portions. Each sbox portion includes a first number of combinational logic gates. Each inverse sbox stage includes a plurality of inverse sbox portions. Each inverse sbox portion includes a second number of combinational logic gates.

    POST-QUANTUM LATTICE-BASED SIGNATURE LATENCY REDUCTION
    15.
    发明公开
    POST-QUANTUM LATTICE-BASED SIGNATURE LATENCY REDUCTION 审中-公开

    公开(公告)号：US20240113888A1

    公开(公告)日：2024-04-04

    申请号：US17936049

    申请日：2022-09-28

    Applicant: Intel Corporation

    Inventor： ZACHARY PEPIN ,  SANTOSH GHOSH ,  MANOJ SASTRY

    IPC: H04L9/32

    CPC classification number: H04L9/3247 ,  H04L9/3271

    Abstract: In one example an apparatus comprises processing circuitry to measure a statistical distance between a marginal distribution of a coordinate of a potential signature (z) over a first interval and a uniform distribution over the first interval and use the statistical distance to determine one or more thresholds of a rejection sampling operation in a lattice-based digital signature algorithm. Other examples may be described.

    HYBRIDIZATION OF DILITHIUM AND FALCON FOR DIGITAL SIGNATURES
    16.
    发明公开
    HYBRIDIZATION OF DILITHIUM AND FALCON FOR DIGITAL SIGNATURES 审中-公开

    公开(公告)号：US20240031164A1

    公开(公告)日：2024-01-25

    申请号：US17814476

    申请日：2022-07-22

    Applicant: Intel Corporation

    Inventor： SANTOSH GHOSH ,  MANOJ SASTRY

    IPC: H04L9/32

    CPC classification number: H04L9/3247 ,  H04L2209/68

    Abstract: In one example an apparatus comprises receive, in a processing platform, an input request from a remote device comprising a digital signature signing or verify function and determine a selected digital signature scheme for the request based at least in part on a determination of whether the processing platform is to apply a signing function or a verify function to the input request. Other examples may be described.

    TECHNOLOGIES FOR LOW-LATENCY CRYPTOGRAPHY FOR PROCESSOR-ACCELERATOR COMMUNICATION
    19.
    发明申请
    TECHNOLOGIES FOR LOW-LATENCY CRYPTOGRAPHY FOR PROCESSOR-ACCELERATOR COMMUNICATION 有权

    公开(公告)号：US20220027288A1

    公开(公告)日：2022-01-27

    申请号：US17496147

    申请日：2021-10-07

    Applicant: Intel Corporation

    Inventor： SANTOSH GHOSH ,  LUIS S. KIDA ,  RESHMA LAL

    IPC: G06F12/14 ,  H04L9/32 ,  G06F21/76 ,  G06F21/60 ,  H04L9/08 ,  G06F9/455 ,  G06F21/57 ,  G06F21/64 ,  H04L12/24 ,  G06F21/79 ,  H04L9/06 ,  G06F9/38 ,  G06F12/0802

    Abstract: Technologies for secure data transfer include a computing device having a processor, an accelerator, and a security engine, such as a direct memory access (DMA) engine or a memory-mapped I/O (MMIO) engine. The computing device initializes the security engine with an initialization vector and a secret key. During initialization, the security engine pre-fills block cipher pipelines and pre-computes hash subkeys. After initialization, the processor initiates a data transfer, such as a DMA transaction or an MMIO request, between the processor and the accelerator. The security engine performs an authenticated cryptographic operation for the data transfer operation. The authenticated cryptographic operation may be AES-GCM authenticated encryption or authenticated decryption. The security engine may perform encryption or decryption using multiple block cipher pipelines. The security engine may calculate an authentication tag using multiple Galois field multipliers. Other embodiments are described and claimed.

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