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    Hybrid Boards with Embedded Planes
    11.
    发明申请
    Hybrid Boards with Embedded Planes 有权

    公开(公告)号：US20210410273A1

    公开(公告)日：2021-12-30

    申请号：US17367674

    申请日：2021-07-06

    Applicant: Intel Corporation

    Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Jenny Shio Yin ONG ,  Seok Ling LIM ,  Chin Lee KUAN ,  Tin Poay CHUAH

    IPC: H05K1/02 ,  H05K3/46

    Abstract: The present disclosure is directed to a hybrid dielectric interconnect stack for a printed circuit board having a first dielectric layer with a first dielectric constant and a first dielectric loss tangent positioned over an intermediate layer, which includes a first dielectric sublayer with a first sublayer dielectric constant and a first sublayer dielectric loss tangent, an embedded conductive layer, and a second dielectric sublayer with a second sublayer dielectric constant and a second sublayer dielectric loss tangent, in which the embedded conductive layer is positioned between the first and second dielectric sublayers, and a second dielectric layer with a second dielectric constant and a second dielectric loss tangent, in which the intermediate layer is positioned between the first and second dielectric layers.

    ASYMMETRICAL LAMINATED CIRCUIT BOARDS FOR IMPROVED ELECTRICAL PERFORMANCE
    15.
    发明申请
    ASYMMETRICAL LAMINATED CIRCUIT BOARDS FOR IMPROVED ELECTRICAL PERFORMANCE 有权

    公开(公告)号：US20210385948A1

    公开(公告)日：2021-12-09

    申请号：US17411064

    申请日：2021-08-25

    Applicant: Intel Corporation

    Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Tin Poay CHUAH ,  Jenny Shio Yin ONG ,  Seok Ling LIM

    IPC: H05K1/11

    Abstract: The present disclosure relates to a printed circuit board assembly including a first circuit board including a first footprint, the first circuit board further includes a plurality of first vertical vias extending between a first side and an opposing second side; a second circuit board including a second footprint smaller than the first footprint, the second circuit board further includes a plurality of second vertical vias extending between a subsequent first side and an opposing subsequent second side; an adhesive layer coupling the first side to the subsequent first side; and a plurality of third vertical vias extending through the first side and the subsequent first side.

    CAPACITOR LOOP STRUCTURE
    16.
    发明申请
    CAPACITOR LOOP STRUCTURE 有权

    公开(公告)号：US20210233875A1

    公开(公告)日：2021-07-29

    申请号：US17229316

    申请日：2021-04-13

    Applicant: Intel Corporation

    Inventor： Jenny Shio Yin ONG ,  Tin Poay CHUAH ,  Chin Lee KUAN

    IPC: H01L23/64 ,  H01L23/498 ,  H05K1/18 ,  H05K1/02 ,  H01L23/50

    Abstract: A capacitor loop substrate assembly may include a substrate with a loop shape, one or more capacitors or other electronic components on the substrate, and an opening in the substrate to allow the capacitor loop substrate assembly to be coupled to an integrated circuit package, such as a package including a die. Interconnects and/or contacts for interconnects may be formed in an integrated circuit package to couple the capacitor loop substrate assembly to the integrated circuit package.

    CAPACITOR LOOP STRUCTURE
    17.
    发明申请
    CAPACITOR LOOP STRUCTURE 审中-公开

    公开(公告)号：US20190279949A1

    公开(公告)日：2019-09-12

    申请号：US16462197

    申请日：2017-11-20

    Applicant: Intel Corporation

    Inventor： Jenny Shio Yin ONG ,  Tin Poay CHUAH ,  Chin Lee KUAN

    IPC: H01L23/64 ,  H01L23/498 ,  H05K1/18

    Abstract: A capacitor loop substrate assembly may include a substrate with a loop shape, one or more capacitors or other electronic components on the substrate, and an opening in the substrate to allow the capacitor loop substrate assembly to be coupled to an integrated circuit package, such as a package including a die. Interconnects and/or contacts for interconnects may be formed in an integrated circuit package to couple the capacitor loop substrate assembly to the integrated circuit package.

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