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公开(公告)号：US20170139864A1
公开(公告)日：2017-05-18
申请号：US15419443
申请日：2017-01-30
Applicant: Intel Corporation
Inventor： Chee Lim Nge , Tod Schiff , Vijayakumar Dibbad , Alan Hallberg
CPC classification number: G06F13/385 , G06F13/382 , G06F13/4068 , G06F13/4282
Abstract: Some embodiments include apparatuses and methods having a node to couple to a serial bus, and a controller to provide a control signal to one of a first circuit path and a second circuit path in order to change electrical termination of a signal at the node between a first electrical termination through the first circuit path during a first mode of the controller and a second electrical termination through the second circuit path during a second mode of the controller. The controller can be arranged to provide the control signal to the first and second circuit paths during the first and second modes without providing another control signal from the controller to the first and second circuit paths during the first and second modes.
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公开(公告)号：US20240088701A1
公开(公告)日：2024-03-14
申请号：US17942392
申请日：2022-09-12
Applicant: Intel Corporation
Inventor： Naoki Matsumura , Colin Carver , Tod Schiff
IPC: H02J7/00 , G01R31/389
CPC classification number: H02J7/007182 , G01R31/389 , H02J7/00304 , H02J7/00308 , H02J7/0048 , H02J7/007194
Abstract: A constant voltage may be used during battery charging to reduce or avoid the formation of a dendrite, such as a stepped constant voltage. For each charging period, each level of the stepped constant voltage may be calculated to ensure a corresponding current level within each period remains below a safe current limit. A voltage transition between any two periods may occur in response to expiration of a predetermined time, or in response to a determination that the current level has fallen below a lower current limit. A current level during each period may be maintained such that the battery heat is maintained below a reference heat level, which may increase battery cycle life (e.g., battery capacity or maximum recharging cycles). The battery heat may be measured directly or indirectly, or may be estimated based on other measured or controlled values.
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公开(公告)号：US11275663B2
公开(公告)日：2022-03-15
申请号：US16896070
申请日：2020-06-08
Applicant: Intel Corporation
Inventor： Alexander Gendler , Nimrod Angel , Ameya Ambardekar , Sapumal Wijeratne , Vikas Vij , Tod Schiff , Alexander Uan-Zo-Li
IPC: G06F1/3296 , G06F11/30 , G06F11/07 , G06F9/30 , G06F9/4401
Abstract: A dedicated pin of a processor or system-on-chip (SoC) is used to indicate whether power level (e.g., charge, voltage, and/or current) of a battery falls below a threshold. The threshold can be predetermined or programmable. The battery is used to provide power to the processor and/or SoC. Upon determining that the power level of the battery falls below the threshold, the processor by-passes the conventional process of entering low performance or power mode, and directly throttles voltage and/or operating frequency of the processor. This allows the processor to continue to operate at low battery power. The fast transition (e.g., approximately 10 μS) from an active state to a low performance or power mode, in accordance with a logic level of the voltage on the dedicated pin, reduces decoupling capacitor design requirements, and makes it possible for the processor to adapt higher package power control settings (e.g., PL4).
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公开(公告)号：US11231761B2
公开(公告)日：2022-01-25
申请号：US16643492
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Philip Lehwalder , Robert Santucci , Tod Schiff
IPC: G06F1/28 , G06F1/3296
Abstract: Power monitoring circuitry is provided to monitor an input system power profile of processing tasks executing on a processing platform. An input is provided to receive from the processing platform, a processing system signal indicating a power being consumed by the processing platform. A counter is provided to store a count value corresponding to an accumulated number or amount of times that a warning threshold condition associated with a warning threshold value is satisfied by the received processing system signal in a count-accumulation time interval. The count value is supplied to a power control circuit of the processing platform via a bus in response to a read request from the power control circuit, the power control circuit being responsive to the count value to control a performance level of the processing platform.
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公开(公告)号：US20210382805A1
公开(公告)日：2021-12-09
申请号：US16896070
申请日：2020-06-08
Applicant: Intel Corporation
Inventor： Alexander Gendler , Nimrod Angel , Ameya Ambardekar , Sapumal Wijeratne , Vikas Vij , Tod Schiff , Alexander Uan-Zo-Li
IPC: G06F11/30 , G06F11/07 , G06F1/3296 , G06F9/4401 , G06F9/30
Abstract: A dedicated pin of a processor or system-on-chip (SoC) is used to indicate whether power level (e.g., charge, voltage, and/or current) of a battery falls below a threshold. The threshold can be predetermined or programmable. The battery is used to provide power to the processor and/or SoC. Upon determining that the power level of the battery falls below the threshold, the processor by-passes the conventional process of entering low performance or power mode, and directly throttles voltage and/or operating frequency of the processor. This allows the processor to continue to operate at low battery power. The fast transition (e.g., approximately 10 μS) from an active state to a low performance or power mode, in accordance with a logic level of the voltage on the dedicated pin, reduces decoupling capacitor design requirements, and makes it possible for the processor to adapt higher package power control settings (e.g., PL4).
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Patent Agency Ranking
公开(公告)号：US09916272B2
公开(公告)日：2018-03-13
申请号：US15419443
申请日：2017-01-30
Applicant: Intel Corporation
Inventor： Chee Lim Nge , Tod Schiff , Vijayakumar Dibbad , Alan Hallberg
CPC classification number: G06F13/385 , G06F13/382 , G06F13/4068 , G06F13/4282
Abstract: Some embodiments include apparatuses and methods having a node to couple to a serial bus, and a controller to provide a control signal to one of a first circuit path and a second circuit path in order to change electrical termination of a signal at the node between a first electrical termination through the first circuit path during a first mode of the controller and a second electrical termination through the second circuit path during a second mode of the controller. The controller can be arranged to provide the control signal to the first and second circuit paths during the first and second modes without providing another control signal from the controller to the first and second circuit paths during the first and second modes.
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公开(公告)号：US20250158442A1
公开(公告)日：2025-05-15
申请号：US18947143
申请日：2024-11-14
Applicant: Intel Corporation
Inventor： Chuen Ming TAN , Venkataramani Gopalakrishnan , Nirmala Bailur , Tai Loong Wong , Yi How Ooi , Sze Geat Pang , Wei Cheang Lau , Tod Schiff , Naoki Matsumura
Abstract: The disclosure provides a device, including: an AC source interface to be coupled to an AC source; a battery interface to be coupled to a battery to be charged by the AC source and discharged for supplying power to the device; and a trigger module to trigger a power supply mode for the device based on a battery-related condition and a device-related condition, wherein the power supply mode includes a reversal power supply mode of using the battery as a primary power source for the device and using the AC source as a secondary power source for the device when the AC source and the battery are both available for providing power to the device.
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18.发明公开公开(公告)号：US20240329705A1
公开(公告)日：2024-10-03
申请号：US18393549
申请日：2023-12-21
Applicant: Intel Corporation
Inventor： Naoki Matsumura , Kirk Jardin , Shirley Arnold Jayachandran , David Woods , Mark Sprenger , Tod Schiff , Jagadish Singh
IPC: G06F1/20 , G06F1/3212 , G06F1/3234
CPC classification number: G06F1/206 , G06F1/3212 , G06F1/3243
Abstract: Techniques for system power control based on a battery's thermal limit and impedance are described. In certain examples, a system includes: a hardware processor that includes a continuous boost power mode; and a power management circuit to couple to a battery, wherein the power management circuit is to: determine heat dissipation for the battery over time when the hardware processor is in the continuous boost power mode, and control power provided to the hardware processor in the continuous boost power mode without exceeding a limit of the heat dissipation over time.
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公开(公告)号：US11342775B2
公开(公告)日：2022-05-24
申请号：US16833113
申请日：2020-03-27
Applicant: Intel Corporation
Inventor： Tod Schiff , Teal Hand , Alexander Uan-Zo-Li
Abstract: Techniques and mechanisms for supplementing power delivery with a battery. In an embodiment, a voltage is provided at a first node with the battery to power a load circuit. A charger is coupled between the first node and a second node, wherein a capacitor is coupled to provide charge to the charger via the second node. In response to detecting a transition of the voltage below a threshold voltage level, controller logic operates switch circuitry of the charger to provide charge from the capacitor. Such operation maintains the voltage in a range of voltage levels which are each above a minimum voltage level required by the load. At least a portion of the range is below the threshold voltage level. In some embodiments, another voltage at the second node provides a basis for generating a control signal to throttle an operation of the load circuit.
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公开(公告)号：US09558144B2
公开(公告)日：2017-01-31
申请号：US14497925
申请日：2014-09-26
Applicant: Intel Corporation
Inventor： Chee Lim Nge , Tod Schiff , Vijayakumar Dibbad , Alan Hallberg
CPC classification number: G06F13/385 , G06F13/382 , G06F13/4068 , G06F13/4282
Abstract: Some embodiments include apparatuses and methods having a node to couple to a serial bus, and a controller to provide a control signal to one of a first circuit path and a second circuit path in order to change electrical termination of a signal at the node between a first electrical termination through the first circuit path during a first mode of the controller and a second electrical termination through the second circuit path during a second mode of the controller. The controller can be arranged to provide the control signal to the first and second circuit paths during the first and second modes without providing another control signal from the controller to the first and second circuit paths during the first and second modes.
Abstract translation: 一些实施例包括具有耦合到串行总线的节点的装置和方法，以及控制器，以向第一电路路径和第二电路路径之一提供控制信号，以便改变位于第一电路路径和第二电路路径之间的节点处的信号的电终端 在控制器的第一模式期间通过第一电路路径进行第一电终接，并且在控制器的第二模式期间通过第二电路路径进行第二电终接。 控制器可以被布置为在第一和第二模式期间向第一和第二电路路径提供控制信号，而不在第一和第二模式期间从控制器向第一和第二电路路径提供另一个控制信号。
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