公开(公告)号：US20250158442A1

公开(公告)日：2025-05-15

申请号：US18947143

申请日：2024-11-14

Applicant: Intel Corporation

Inventor： Chuen Ming TAN ,  Venkataramani Gopalakrishnan ,  Nirmala Bailur ,  Tai Loong Wong ,  Yi How Ooi ,  Sze Geat Pang ,  Wei Cheang Lau ,  Tod Schiff ,  Naoki Matsumura

IPC: H02J7/06 ,  H02J7/00 ,  H02J7/34

Abstract: The disclosure provides a device, including: an AC source interface to be coupled to an AC source; a battery interface to be coupled to a battery to be charged by the AC source and discharged for supplying power to the device; and a trigger module to trigger a power supply mode for the device based on a battery-related condition and a device-related condition, wherein the power supply mode includes a reversal power supply mode of using the battery as a primary power source for the device and using the AC source as a secondary power source for the device when the AC source and the battery are both available for providing power to the device.

公开(公告)号：US20210212205A1

公开(公告)日：2021-07-08

申请号：US17212016

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Khai Ern See ,  Jia Lin Liew ,  Tin Poay Chuah ,  Chee How Lim ,  Yi How Ooi

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/42 ,  H05K3/00

Abstract: Techniques for power tunnels on circuit boards are disclosed. A power tunnel may be created in a circuit board by drilling through non-conductive layers to a conductive trace and then filling in the hole with a conductor. A power tunnel can have a high cross-sectional area and can carry a larger amount of current than an equivalent-width trace, reducing the area on a circuit board required to carry that amount of current.

公开(公告)号：US12156331B2

公开(公告)日：2024-11-26

申请号：US17212016

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Khai Ern See ,  Jia Lin Liew ,  Tin Poay Chuah ,  Chee How Lim ,  Yi How Ooi

IPC: H05K1/02 ,  H01L21/3105 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42

Abstract: Techniques for power tunnels on circuit boards are disclosed. A power tunnel may be created in a circuit board by drilling through non-conductive layers to a conductive trace and then filling in the hole with a conductor. A power tunnel can have a high cross-sectional area and can carry a larger amount of current than an equivalent-width trace, reducing the area on a circuit board required to carry that amount of current.

公开(公告)号：US20230093974A1

公开(公告)日：2023-03-30

申请号：US17448798

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Chuen Ming Tan ,  Venkataramani Gopalakrishnan ,  Nirmala Bailur ,  Tai Loong Wong ,  Yi How Ooi ,  Sze Geat Pang ,  Wei Cheang Lau

IPC: G06F1/3234 ,  G06F1/3212 ,  G06F1/26

Abstract: In an embodiment, a computing system for selecting a power mode may include: a system load, a battery, a power converter to receive external power and provide output power, and a processor to: monitor a charge level of the battery while the computing system is in a converter power mode, where the converter power mode comprises to power the system load and charge the battery from the output power of the power converter; and in response to a determination that the charge level of the battery is within a battery condition range, cause the computing system to switch from the converter power mode to a battery power mode, where the battery power mode comprises, during a connection of the power converter to the external power, to disconnect the battery from the power converter and power the system load from output power of the battery.