-
11.发明授权公开(公告)号：US12261622B2
公开(公告)日：2025-03-25
申请号：US17358152
申请日：2021-06-25
Applicant: Intel Corporation
Inventor： Michael Kalcher , Daniel Gruber , Martin Clara
Abstract: Circuitry for digital-to-analog conversion is provided. The circuitry includes a driver circuit and a weighting resistor circuit coupled to an output of the driver circuit. The weighting resistor circuit includes a first resistive sub-circuit coupled to the output of the driver circuit and an intermediate node. The weighting resistor further includes a second resistive sub-circuit coupled to the intermediate node and a common node. Further, the weighting circuit includes a third resistive sub-circuit coupled to the intermediate node and an output of the circuitry. The resistivity of the second resistive sub-circuit is equal to or smaller than the resistivity of the first resistive sub-circuit.
-
公开(公告)号：US20250007279A1
公开(公告)日：2025-01-02
申请号：US18215033
申请日：2023-06-27
Applicant: Intel Corporation
Inventor： Susanne Heber , Daniel Gruber , Krzysztof Domanski , Martin Clara
IPC: H02H9/04
Abstract: An integrated circuit device includes a signal pad, an inductor coupled in series with the signal pad, and an electrostatic discharge (ESD) protection circuit distributed before and after the inductor to provide ESD protection for an ESD event on the signal pad. Other examples are disclosed and claimed.
-
公开(公告)号：US10938404B1
公开(公告)日：2021-03-02
申请号：US16728163
申请日：2019-12-27
Applicant: Intel Corporation
Inventor： Ramon Sanchez , Kameran Azadet , Martin Clara , Daniel Gruber
Abstract: A digital-to-analog converter is provided. The digital-to-analog converter comprises an input configured to receiving a first digital control code for controlling a plurality of digital-to-analog converter cells. Further, the digital-to-analog converter comprises a code converter circuit configured to converter the first digital control code to a second digital control code. Further, the digital-to-analog converter comprises a shift code generation circuit configured to generate a shift code based on a code difference between the first digital control code and a third digital control code. The digital-to-analog converter additionally comprises a bit-shifter circuit configured to bit-shift the second digital control code based on the shift code in order to obtain a modified second digital control code. The digital-to-analog converter comprises a cell activation circuit configured to selectively activate one or more of the plurality of digital-to-analog converter cells based on the modified second digital control code. Each activated digital-to-analog converter cell is configured to output a respective cell output signal. Further, the digital-to-analog converter comprises an output configured to output an analog output signal based on the cell output signals.
-
14.发明授权公开(公告)号：US12278649B2
公开(公告)日：2025-04-15
申请号：US17358131
申请日：2021-06-25
Applicant: Intel Corporation
Inventor： Ramon Sanchez , Kameran Azadet , Martin Clara , Daniel Gruber
Abstract: A processing device is provided. The processing device comprises one or more interfaces configured to transmit information to a nonlinear device and processing circuitry configured to control the one or more interfaces and to. Further, the processing circuitry is configured to transmit an excitation signal to the nonlinear device and to receive response information from the nonlinear device. Further, the processing circuitry is configured to determine a linear response of the nonlinear device based on the response information and to determine a nonlinear response of the nonlinear device based on the determined linear response.
-
公开(公告)号：US12170526B2
公开(公告)日：2024-12-17
申请号：US18054628
申请日：2022-11-11
Applicant: Intel Corporation
Inventor： Daniel Gruber , Kameran Azadet , Martin Clara , Marc Jan Georges Tiebout
Abstract: A semiconductor device comprising at least one transmit path is provided. The transmit path comprises an input node for receiving a digital baseband signal. Further, the transmit path comprises digital mixer circuitry coupled to the input node and configured to generate an upconverted digital baseband signal by upconverting a frequency of the digital baseband signal. Additionally, the transmit path comprises Digital-to-Analog Converter (DAC) circuitry coupled to the digital mixer circuitry and configured to generate an analog radio frequency signal based on the upconverted digital baseband signal. The transmit path comprises first analog mixer circuitry coupleable to an output of the DAC circuitry, and second analog mixer circuitry coupleable to the output of the DAC circuitry. Further, the transmit path comprises a first output node coupleable to an output of the first analog mixer circuitry, and a second output node coupleable to an output of the second analog mixer circuitry.
-
Patent Agency Ranking
公开(公告)号：US11949446B2
公开(公告)日：2024-04-02
申请号：US16912741
申请日：2020-06-26
Applicant: Intel Corporation
Inventor： Daniel Gruber , Mark Elzinga , Martin Clara
CPC classification number: H04B1/582 , H01Q1/246 , H01Q23/00 , H04B1/0475 , H04B2001/0433
Abstract: The present disclosure relates to a concept for a transformer, a transmitter circuit, a semiconductor chip, a semiconductor package, a base station, a mobile device and a method for a radio frequency transmitter. The transformer for a radio frequency transmitter circuit comprises a primary coil and a secondary coils, which are configured to receive an input signal and to provide an output signal, and a ternary coil configured to provide a feedback signal.
-
公开(公告)号：US11528182B2
公开(公告)日：2022-12-13
申请号：US17351288
申请日：2021-06-18
Applicant: Intel Corporation
Inventor： Kameran Azadet , Martin Clara , Daniel Gruber , Christian Lindholm , Hundo Shin
Abstract: An Analog-to-Digital Converter, ADC, system is provided. The ADC system comprises a plurality of ADC circuits and a first input for receiving a transmit signal of a transceiver. One ADC circuit of the plurality of ADC circuits is coupled to the first input and configured to provide first digital data based on the transmit signal. The ADC system further comprises a second input for receiving a receive signal of the transceiver. The other ADC circuits of the plurality of ADC circuits are coupled to the second input, wherein the other ADC circuits of the plurality of ADC circuits are time-interleaved and configured to provide second digital data based on the receive signal. Additionally, the ADC system comprises a first output configured to output digital feedback data based on the first digital data, and a second output configured to output digital receive data based on the second digital data.
-
公开(公告)号：US11038516B1
公开(公告)日：2021-06-15
申请号：US16886817
申请日：2020-05-29
Applicant: Intel Corporation
Inventor： Kameran Azadet , Ramon Sanchez , Albert Molina , Martin Clara , Daniel Gruber , Matteo Camponeschi
Abstract: An apparatus and method for analog-to-digital conversion. The apparatus includes a first analog-to-digital converter (ADC), a second ADC, and a calibration unit. The first ADC is configured to sample an input analog signal at a first sampling frequency. The second ADC is configured to sample the input analog signal at a second sampling frequency. The second sampling frequency is a fraction of the first sampling frequency. The calibration unit is configured to correct a distortion incurred in an output of the first ADC based on an output of the second ADC. The first ADC may be a time-interleaved ADC. The second ADC may be an extra sub-ADC of the time-interleaved ADC. The second ADC may be configured to sample the input analog signal at random sampling phases. A dithering noise may be added to the input analog signal of the second ADC. The calibration unit may be a non-linear equalizer.
-
19.发明授权公开(公告)号：US12074606B2
公开(公告)日：2024-08-27
申请号：US17131811
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Daniel Gruber , Christian Lindholm , Martin Clara , Giacomo Cascio
IPC: H03M1/08 , H03K19/003 , H03K19/0185 , H04B1/12
CPC classification number: H03M1/0827 , H03K19/00384 , H03K19/018578 , H04B1/12
Abstract: A reference buffer circuit for an analog-to-digital converter is provided. The reference buffer circuit includes a first input node configured to receive a first bias signal of a first polarity from a first signal line. Further, the reference buffer circuit includes a second input node configured to receive a second bias signal of a second polarity from a second signal line. Additionally, the reference buffer circuit includes a first output node configured to output a first reference signal of the first polarity. A first buffer amplifier is coupled between the first input node and the first output node. The reference buffer circuit includes in addition a second output node configured to output a second reference signal of the second polarity. A second buffer amplifier is coupled between the second input node and the second output node. Further, the reference buffer circuit includes a first coupling path comprising a first capacitive element. The first coupling path is coupled between the first output node and the second input node. In addition, the reference buffer circuit includes a second coupling path comprising a second capacitive element. The second coupling path is coupled between the second output node and the first input node.
-
公开(公告)号：US12034452B2
公开(公告)日：2024-07-09
申请号：US17132000
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Daniel Gruber , Michael Kalcher , Martin Clara
Abstract: A Digital-to-Analog Converter (DAC) is provided. The DAC includes a code converter circuit configured to sequentially receive first digital control codes for controlling N digital-to-analog converter cells. N is an integer greater than one. The code converter circuit is further configured to convert the first digital control codes to second digital control codes. Additionally, the DAC includes a bit-shifter circuit configured to receive shift codes for the second digital control codes. The shift codes are obtained using dynamic element matching and indicate a respective circular shift by ri bit positions for the i-th second digital control code, wherein ri is an integer smaller than N−1. The bit-shifter circuit is further configured to generate third digital control codes by circularly shifting the second digital codes based on the shift codes. In addition, the DAC includes a cell activation circuit configured to selectively activate one or more of the N digital-to-analog converter cells based on the third digital control codes.
-
-
-
-
-
-
-
-
-
Search Results
33
records
(took 0.023 seconds)
