公开(公告)号：US20180232273A1

公开(公告)日：2018-08-16

申请号：US15951483

申请日：2018-04-12

Applicant: Invensas Corporation

Inventor： William C. Plants

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52 ,  G11C29/04

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0679 ,  G06F3/0688 ,  G11C29/52 ,  G11C2029/0411

Abstract: The invention pertains to non-volatile memory devices, and more particularly to advantageously encoding data in non-volatile devices in a flexible manner by both NVM manufacturers and NVM users. Multiple methods of preferred state encoding (PSE) and/or error correction code (ECC) encoding may be used in different pages or blocks in the same NVM device for different purposes which may be dependent on the nature of the data to be stored.

公开(公告)号：US20180121283A1

公开(公告)日：2018-05-03

申请号：US15713439

申请日：2017-09-22

Applicant: Invensas Corporation

Inventor： William C. Plants

IPC: G06F11/10 ,  H03M13/29 ,  G11C29/52

CPC classification number: G11C29/52 ,  G06F11/1012 ,  G06F11/1076 ,  G11C5/025 ,  G11C5/04 ,  G11C11/401 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/783

Abstract: The invention pertains to semiconductor memories, and more particularly to enhancing the reliability of stacked memory devices. Apparatuses and methods are described for implementing RAID-style error correction to increase the reliability of the stacked memory devices.

公开(公告)号：US09299398B2

公开(公告)日：2016-03-29

申请号：US14683687

申请日：2015-04-10

Applicant: Invensas Corporation

Inventor： David Edward Fisch ,  William C. Plants ,  Kent Stalnaker

IPC: G11C5/14 ,  G11C7/00 ,  G11C29/52 ,  G11C7/02 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/06 ,  G11C11/4091

CPC classification number: G11C11/4091 ,  G11C7/00 ,  G11C7/02 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1069 ,  G11C7/1096 ,  G11C11/4087 ,  G11C11/4096 ,  G11C29/52

Abstract: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.

公开(公告)号：US10169143B2

公开(公告)日：2019-01-01

申请号：US15951483

申请日：2018-04-12

Applicant: Invensas Corporation

Inventor： William C. Plants

IPC: G11C29/00 ,  G06F11/10 ,  G06F3/06 ,  G11C29/52 ,  G11C29/04

Abstract: The invention pertains to non-volatile memory devices, and more particularly to advantageously encoding data in non-volatile devices in a flexible manner by both NVM manufacturers and NVM users. Multiple methods of preferred state encoding (PSE) and/or error correction code (ECC) encoding may be used in different pages or blocks in the same NVM device for different purposes which may be dependent on the nature of the data to be stored.

公开(公告)号：US10083079B2

公开(公告)日：2018-09-25

申请号：US15713439

申请日：2017-09-22

Applicant: Invensas Corporation

Inventor： William C. Plants

IPC: G11C7/00 ,  G06F11/10 ,  H03M13/29 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G06F11/1076 ,  G11C5/025 ,  G11C5/04 ,  G11C11/401 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/783 ,  H03M13/2906

Abstract: The invention pertains to semiconductor memories, and more particularly to enhancing the reliability of stacked memory devices. Apparatuses and methods are described for implementing RAID-style error correction to increase the reliability of the stacked memory devices.

公开(公告)号：US09778984B1

公开(公告)日：2017-10-03

申请号：US15340883

申请日：2016-11-01

Applicant: Invensas Corporation

Inventor： William C. Plants

IPC: G11C7/00 ,  G06F11/10 ,  G11C29/52 ,  H03M13/29

CPC classification number: G11C29/52 ,  G06F11/1012 ,  G06F11/1076 ,  G11C5/025 ,  G11C5/04 ,  G11C11/401 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/783

Abstract: The invention pertains to semiconductor memories, and more particularly to enhancing the reliability of stacked memory devices. Apparatuses and methods are described for implementing RAID-style error correction to increase the reliability of the stacked memory devices.

公开(公告)号：US20170117030A1

公开(公告)日：2017-04-27

申请号：US15019788

申请日：2016-02-09

Applicant: Invensas Corporation

Inventor： David Edward Fisch ,  William C. Plants

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/406 ,  G11C11/40626 ,  G11C11/4087 ,  G11C29/025 ,  G11C29/06 ,  G11C29/789 ,  G11C2029/0403

Abstract: The invention pertains to mitigation of row hammer attacks in DRAM integrated circuits. Apparatus and methods are disclosed for an embedded target row refresh (TRR) solution with modest overhead. In operation it is nearly transparent to the user. Except for enablement via the mode register and an increase in the average refresh rate on the order of half of one percent, no further user action is required. The stream of row addresses accompanying ACTIVE commands is monitored and filtered to only track addresses that occur at a dangerous rate and reject addresses that occur at less than a dangerous rate.