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公开(公告)号：US09117022B1
公开(公告)日：2015-08-25
申请号：US13352090
申请日：2012-01-17
IPC分类号： G06F13/36 , G06F13/364
CPC分类号： G06F13/364
摘要： Systems and methods for increasing speed and reducing area for arbitration logic in an integrated circuit (IC) are provided. For example, in one embodiment, a method includes arbitrating at least one master request in a first level of arbitration blocks. A second level of arbitration blocks arbitrates at least two arbitration blocks from the first level. A first level of multiplexers multiplex at least one master payload based at least in part upon the arbitration of the first level of arbitration blocks. A second level of multiplexers multiplex at least two signals propagated from the first level of multiplexers.
摘要翻译： 提供了用于提高集成电路（IC）中仲裁逻辑的速度和减小面积的系统和方法。 例如，在一个实施例中，一种方法包括在第一级仲裁块中仲裁至少一个主请求。 第二级仲裁块从第一级仲裁至少两个仲裁块。 第一级复用器至少部分地基于第一级仲裁块的仲裁来复用至少一个主有效载荷。 第二级复用器复用从第一级复用器传播的至少两个信号。
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公开(公告)号：US10224908B1
公开(公告)日：2019-03-05
申请号：US13329089
申请日：2011-12-16
摘要： An integrated circuit may include path delay calibration circuitry. The calibration circuitry may be configured to calibrate respective delay paths so that data and control signals travelling through the respective delay paths experience proper propagation delays during normal user operation. The calibration circuitry may include a high frequency error calibration circuit, a monitoring circuit, and a calibration processing circuit. The high frequency error calibration circuit may be used to compute first calibration settings that take into account jitter and process variations. The monitoring circuit may be used to measure a proxy parameter of interest. The processing circuit may be used to compute an offset based at least partly on the measured value of the proxy parameter. The offset may be applied to the first calibration settings to obtain second calibration settings, which can be used to configure the respective delay paths.
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公开(公告)号：US09229888B1
公开(公告)日：2016-01-05
申请号：US13562124
申请日：2012-07-30
CPC分类号： G06F13/1668 , G06F15/7867 , G06F17/5054
摘要： Architecture, systems, and methods for developing, an area-efficient dynamically-configurable memory controller are described. The architecture, systems and methods may provide savings in terms of surface area required for implementing a dynamically configurable hardened memory controller or controllers.
摘要翻译： 描述了用于开发的架构，系统和方法，区域高效的可动态配置的存储器控制器。 架构，系统和方法可以在实现可动态配置的硬化存储器控制器或控制器所需的表面积方面节省。
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公开(公告)号：US08977810B2
公开(公告)日：2015-03-10
申请号：US13441706
申请日：2012-04-06
CPC分类号： G06F13/1626
摘要： Systems and methods for using memory commands are described. The systems include a memory controller. The memory controller receives a plurality of user transactions. The memory controller converts each user transaction into one or more row and column memory commands. The memory controller reorders the memory commands associated with the plurality of user transactions before sending the memory commands to a memory device.
摘要翻译： 描述了使用存储器命令的系统和方法。 这些系统包括一个内存控制器。 存储器控制器接收多个用户事务。 存储器控制器将每个用户事务转换成一个或多个行和列存储器命令。 在将存储器命令发送到存储器设备之前，存储器控制器重新排列与多个用户事务相关联的存储器命令。
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15.发明授权公开(公告)号：US08929162B1
公开(公告)日：2015-01-06
申请号：US13531430
申请日：2012-06-22
CPC分类号： G11C7/1051 , G11C7/1066
摘要： In a memory interface circuit (e.g., a programmable logic device), a clock or strobe (DQS) signal can be gated using a clock-like signal that can also be used to sample the DQS signal. Furthermore, both the rising and falling edges of the DQS signal can be sampled using the clock-like signal.
摘要翻译： 在存储器接口电路（例如，可编程逻辑器件）中，时钟或选通（DQS）信号可以使用也可用于采样DQS信号的类似时钟的信号来选通。 此外，可以使用类似时钟的信号对DQS信号的上升沿和下降沿进行采样。
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公开(公告)号：US20120260032A1
公开(公告)日：2012-10-11
申请号：US13441706
申请日：2012-04-06
IPC分类号： G06F12/00
CPC分类号： G06F13/1626
摘要： Systems and methods for using memory commands are described. The systems include a memory controller. The memory controller receives a plurality of user transactions. The memory controller converts each user transaction into one or more row and column memory commands. The memory controller reorders the memory commands associated with the plurality of user transactions before sending the memory commands to a memory device.
摘要翻译： 描述了使用存储器命令的系统和方法。 这些系统包括一个内存控制器。 存储器控制器接收多个用户事务。 存储器控制器将每个用户事务转换成一个或多个行和列存储器命令。 在将存储器命令发送到存储器设备之前，存储器控制器重新排列与多个用户事务相关联的存储器命令。
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公开(公告)号：US08813018B1
公开(公告)日：2014-08-19
申请号：US13646559
申请日：2012-10-05
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A logic design system operable to configure an integrated circuit device using custom logic design data is disclosed. The disclosed logic design system includes a computer-aided design tool that may be used to determine a memory space estimate based on a custom logic design data analysis. A memory size analysis may be performed on the custom logic design data to determine the maximum amount of stack memory that is required to execute procedures in the device. The logic design system may also monitor for changing memory requirements of the custom logic design. The logic design system may configure the device with the custom logic design data based on the memory space estimate.
摘要翻译： 公开了一种用于使用定制逻辑设计数据配置集成电路设备的逻辑设计系统。 所公开的逻辑设计系统包括计算机辅助设计工具，其可以用于基于定制逻辑设计数据分析来确定存储器空间估计。 可以对自定义逻辑设计数据执行存储器大小分析，以确定在设备中执行过程所需的堆栈存储器的最大量。 逻辑设计系统还可以监视定制逻辑设计的内存需求。 逻辑设计系统可以基于存储器空间估计来配置具有定制逻辑设计数据的设备。
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18.发明授权Methods and systems for improving a maximum operating frequency of a PLD having a shift register within an embedded memory block 有权用于改善在嵌入式存储器块内具有移位寄存器的PLD的最大工作频率的方法和系统公开(公告)号：US07821295B1
公开(公告)日：2010-10-26
申请号：US12413404
申请日：2009-03-27
申请人： Gordon Raymond Chiu
发明人： Gordon Raymond Chiu
IPC分类号： G11C7/00 , G06F7/38 , H03K19/173
CPC分类号： H03K19/17776 , H03K19/1776
摘要： A method for improving a maximum operating frequency of an integrated circuit including a first shift register within a first random access memory (RAM) block is described. The method includes improving the maximum operating frequency by finding the first shift register implemented within the first RAM block.
摘要翻译： 描述了一种用于提高包括第一随机存取存储器（RAM）块内的第一移位寄存器的集成电路的最大工作频率的方法。 该方法包括通过找到在第一RAM块内实现的第一移位寄存器来提高最大工作频率。
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