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    UNIFORM SEEDING TO CONTROL GRAIN AND DEFECT DENSITY OF CRYSTALLIZED SILICON FOR USE IN SUB-MICRON THIN FILM TRANSISTORS
    12.
    发明申请
    UNIFORM SEEDING TO CONTROL GRAIN AND DEFECT DENSITY OF CRYSTALLIZED SILICON FOR USE IN SUB-MICRON THIN FILM TRANSISTORS 审中-公开
    用于控制颗粒的均匀性和缺陷密度用于亚微米薄膜晶体管的结晶硅密度

    公开(公告)号：US20070105352A1

    公开(公告)日：2007-05-10

    申请号：US11615819

    申请日：2006-12-22

    申请人： Shuo Gu ,  James Cleeves

    发明人： Shuo Gu ,  James Cleeves

    IPC分类号： H01L29/76 ,  H01L21/20

    CPC分类号： H01L21/02675 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2022 ,  H01L29/6675 ,  H01L29/78672

    摘要： A method to create a polysilicon layer with large grains and uniform grain density is described. A first amorphous silicon layer is formed. A crystallizing agent is selectively introduced in a substantially symmetric pattern, preferably symmetric in two dimensions, across an area of the first amorphous layer. The crystallizing agent may be, for example, silicon nuclei, germanium, or laser energy. A mask layer is formed on the amorphous silicon layer, and holes etched in the mask layer in a symmetric pattern to expose the amorphous layer to, for example, silicon nuclei or germanium) only in the holes. The mask layer is removed and a second amorphous layer formed on the first. If laser energy is used, no mask layer or second amorphous layer is generally used. The wafer is annealed to form a polysilicon layer with substantially no amorphous silicon remaining between the grains.

    摘要翻译： 描述了制造具有大晶粒和均匀晶粒密度的多晶硅层的方法。 形成第一非晶硅层。 选择性地将结晶剂以跨越第一非晶层的区域的基本上对称的图案（优选在二维对称的方式）引入。 结晶剂可以是例如硅核，锗或激光能。 在非晶硅层上形成掩模层，并且以对称图案在掩模层中蚀刻出孔，以将非晶层暴露于例如硅核或锗）仅在孔中。 除去掩模层，在第一层上形成第二非晶层。 如果使用激光能量，则通常不使用掩模层或第二非晶层。 将晶片退火以形成在晶粒之间基本上不存在无定形硅的多晶硅层。

    Memory cell with high-K antifuse for reverse bias programming
    13.
    发明申请
    Memory cell with high-K antifuse for reverse bias programming 有权
    具有高K反熔丝的存储单元用于反向偏置编程

    公开(公告)号：US20070002603A1

    公开(公告)日：2007-01-04

    申请号：US11174240

    申请日：2005-07-01

    申请人： James Cleeves

    发明人： James Cleeves

    IPC分类号： G11C17/00

    CPC分类号： G11C17/16 ,  G11C11/5692 ,  G11C13/0069 ,  G11C17/165 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2213/71 ,  G11C2213/72

    摘要： An integrated circuit and associated method of programming are provided. Such integrated circuit includes a memory cell with a diode and an antifuse in communication with the diode. The antifuse is constructed to include a high-K dielectric material with a K greater than 3.9. Further, the memory cell is programmed utilizing a programming pulse that reverse biases the diode thereof.

    摘要翻译： 提供了集成电路和相关的编程方法。 这种集成电路包括具有二极管的存储单元和与二极管连通的反熔丝。 反熔丝被构造成包括K大于3.9的高K电介质材料。 此外，使用反向偏置其二极管的编程脉冲对存储单元进行编程。

    Optimization of critical dimensions and pitch of patterned features in and above a substrate
    16.
    发明申请
    Optimization of critical dimensions and pitch of patterned features in and above a substrate 有权
    优化衬底中和图案上的图案特征的临界尺寸和间距

    公开(公告)号：US20050121790A1

    公开(公告)日：2005-06-09

    申请号：US10728437

    申请日：2003-12-05

    申请人： James Cleeves ,  Roy Scheuerlein

    发明人： James Cleeves ,  Roy Scheuerlein

    IPC分类号： H01L23/528 ,  H01L27/105 ,  H01L23/48 ,  H01L23/52 ,  H01L29/76 ,  H01L31/113

    CPC分类号： H01L27/105 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region.

    摘要翻译： 在使用光刻和蚀刻技术的不同器件级别和那些器件级别的区域中，使用不同且优化的临界尺寸形成管芯。 本发明的一个方面提供了形成在衬底上的存储器阵列，其中驱动电路形成在衬底中。 存储器阵列的一个级别包括例如平行轨道和扇出区域。 希望使轨道的密度最大化并最小化整个存储器阵列的光刻成本。 这可以通过以比它下面的CMOS电路更紧的间距形成轨道来实现，从而允许在形成CMOS时使用更便宜的光刻工具，并且类似地通过优化用于器件级别的光刻和蚀刻技术以在 轨道，并且在不太关键的扇出区域更放松。

    Spark plug
    17.
    发明申请
    Spark plug 失效
    火花塞

    公开(公告)号：US20050057132A1

    公开(公告)日：2005-03-17

    申请号：US10663162

    申请日：2003-09-15

    申请人： James Cleeves

    发明人： James Cleeves

    IPC分类号： H01T13/46 ,  H01T13/50 ,  H01T13/20

    CPC分类号： H01T13/467 ,  H01T13/462 ,  H01T13/50

    摘要： A spark plug is disclosed having at least one main electrode and at least one secondary electrode. The gaps associated with the secondary electrodes are between one third and two thirds the optimum gap distance. Resistors associated with the secondary electrodes control the current flow and therefore the voltage on the electrodes.

    摘要翻译： 公开了具有至少一个主电极和至少一个次级电极的火花塞。 与次级电极相关的间隙是最佳间隙距离的三分之一和三分之二。 与次级电极相关联的电阻器控制电流，因此控制电极上的电压。