-
公开(公告)号：US07096433B2
公开(公告)日：2006-08-22
申请号：US10703562
申请日：2003-11-10
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method and chip design are provided for reducing power consumption. A first functional block having a phase logic circuit may be provided in a first area of a chip. A second functional block having an edge-triggered circuit may be provided in a second area of the chip. Edge-triggered circuits within the second functional block may be replaced with dual edge-triggered circuits. Phase logic circuits may be clocked by a full frequency clock signal and dual edge-triggered circuits may be clocked by a half-frequency clock signal.
摘要翻译： 提供了一种降低功耗的方法和芯片设计。 具有相位逻辑电路的第一功能块可以设置在芯片的第一区域中。 具有边缘触发电路的第二功能块可以设置在芯片的第二区域中。 第二功能块内的边沿触发电路可以用双边沿触发电路代替。 相位逻辑电路可以由全频时钟信号来计时，并且双边沿触发电路可以由半频时钟信号来计时。
-
公开(公告)号：US06622255B1
公开(公告)日：2003-09-16
申请号：US09660808
申请日：2000-09-13
申请人： Nasser A. Kurd , Javed Barkatullah
发明人： Nasser A. Kurd , Javed Barkatullah
IPC分类号： G06F112
CPC分类号： H03D13/003 , G06F1/10 , H03K5/133 , H03K5/15013 , H03L7/07 , H03L7/081 , H03L7/0814 , H03L7/089
摘要： A skew measure circuit, an exclusion circuit, and an up/down counter are connected to form a skew detection circuit. The skew measure circuit asserts a first output signal if a first input clock leads a second input clock, and asserts a second output signal if the second clock leads the first clock. The exclusion circuit provides first and second digital pulse signals that represent the outputs of the skew measure circuit. The exclusion circuit also prevents the states of these pulse signals from changing, so long as the skew measure circuit is experiencing metastability. The up/down counter's count is incremented in response to the first pulse signal and decremented in response to the other pulse signal.
摘要翻译： 连接偏斜测量电路，排除电路和升降计数器以形成偏斜检测电路。 如果第一输入时钟引导第二输入时钟，则偏斜测量电路确定第一输出信号，并且如果第二时钟引导第一时钟，则断言第二输出信号。 排除电路提供表示偏斜测量电路的输出的第一和第二数字脉冲信号。 只要偏差测量电路正在经历亚稳态，排除电路也可以防止这些脉冲信号的状态改变。 升/减计数器的计数响应于第一脉冲信号而增加，并响应于另一个脉冲信号递减。
-
公开(公告)号：US07562316B2
公开(公告)日：2009-07-14
申请号：US11486030
申请日：2006-07-14
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method and chip design are provided for reducing power consumption. A first functional block having a phase logic circuit may be provided in a first area of a chip. A second functional block having an edge-triggered circuit may be provided in a second area of the chip. Edge-triggered circuits within the second functional block may be replaced with dual edge-triggered circuits. Phase logic circuits may be clocked by a full frequency clock signal and dual edge-triggered circuits may be clocked by a half-frequency clock signal.
摘要翻译： 提供了一种降低功耗的方法和芯片设计。 具有相位逻辑电路的第一功能块可以设置在芯片的第一区域中。 具有边缘触发电路的第二功能块可以设置在芯片的第二区域中。 第二功能块内的边沿触发电路可以用双边沿触发电路代替。 相位逻辑电路可以由全频时钟信号来计时，并且双边沿触发电路可以由半频时钟信号来计时。
-
14.发明授权Method and apparatus for optimizing clock distribution to reduce the effect of power supply noise 失效优化时钟分配的方法和装置，以减少电源噪声的影响公开(公告)号：US06934872B2
公开(公告)日：2005-08-23
申请号：US10021058
申请日：2001-12-19
CPC分类号： G06F1/10
摘要： A method and apparatus for optimizing clock distribution in a circuit to reduce the effect of power supply noise. Parameters are determined including: a response curve of a power source for a circuit, a delay sensitivity of a clock net in the circuit to the power source, a delay sensitivity of a data net in the circuit to the power source, a data delay for the data net, and a clock delay for the clock net. The clock delay is adjusted to reduce the effect of power supply noise on the data net. The adjusting is based on the response curve of the power source, the delay sensitivity of the clock net, the delay sensitivity of the data net, the data delay, and the clock delay. The adjusting includes adding a pre-distribution clock delay.
摘要翻译： 一种用于优化电路中的时钟分布以减少电源噪声的影响的方法和装置。 确定参数，包括：电路的电源的响应曲线，到电源的电路中的时钟网络的延迟灵敏度，电路中的数据网到电源的延迟灵敏度，数据延迟 数据网和时钟网的时钟延迟。 调整时钟延迟以减少电源噪声对数据网的影响。 调整是基于电源的响应曲线，时钟网络的延迟灵敏度，数据网络的延迟灵敏度，数据延迟和时钟延迟。 调整包括添加预分配时钟延迟。
-
15.发明授权Method and apparatus for synchronizing clock signals in a multiple die circuit including a stop clock feature 失效用于在包括停止时钟特征的多芯片电路中同步时钟信号的方法和装置
公开(公告)号：US5706485A
公开(公告)日：1998-01-06
申请号：US536195
申请日：1995-09-29
CPC分类号： G06F1/10 , H03K5/15066 , H03L7/00
摘要： A circuit contains a microprocessor die, containing a microprocessor, and a cache memory die, containing a cache memory, for operation in conjunction with the microprocessor. A microprocessor clock and a cache memory clock are generated for operation of the microprocessor and the cache memory, respectively. The microprocessor and cache memory clocks are generated on the microprocessor die, and the cache memory clock is transmitted to the cache memory die. In order to transmit data between the microprocessor die and the cache memory die, clock cycles are designated. The microprocessor clock and the cache memory clock are synchronized to the clock cycles including compensation for the propagation delay between the two dies. The microprocessor includes a stop clock function which halts the cache memory clock and the microprocessor clock on the same clock cycle so that data integrity, in both the microprocessor and cache memory, are maintained. In order to provide functional operation over a range of clock cycle frequencies, the data, from cache memory die, becomes valid on the falling edge of the cache clock signal, and is subsequently sampled, in the same clock cycle, on the rising edge of the microprocessor clock.
摘要翻译： 电路包含微处理器管芯，其中包含微处理器和高速缓冲存储器管芯，其包含用于与微处理器结合操作的高速缓冲存储器。 生成微处理器时钟和高速缓冲存储器时钟用于微处理器和高速缓冲存储器的操作。 微处理器和高速缓冲存储器时钟在微处理器管芯上产生，高速缓存存储器时钟被传送到高速缓存存储器管芯。 为了在微处理器管芯和高速缓冲存储器管芯之间传送数据，指定时钟周期。 微处理器时钟和高速缓冲存储器时钟与时钟周期同步，包括两个管芯之间的传播延迟的补偿。 微处理器包括停止时钟功能，该功能在相同的时钟周期中停止高速缓冲存储器时钟和微处理器时钟，从而保持微处理器和高速缓存中的数据完整性。 为了在一系列时钟周期频率上提供功能操作，来自高速缓存存储器管芯的数据在高速缓存时钟信号的下降沿变为有效，随后在相同的时钟周期中在 微处理器时钟。
-
-
-
-
搜索结果
15 条记录 (耗时 0.019 秒)