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11.发明授权公开(公告)号：US08536034B2
公开(公告)日：2013-09-17
申请号：US13216921
申请日：2011-08-24
申请人： Stefan Flachowsky , Ralf Illgen , Thilo Scheiper , Jan Hoentschel
发明人： Stefan Flachowsky , Ralf Illgen , Thilo Scheiper , Jan Hoentschel
IPC分类号： H01L21/425
CPC分类号： H01L21/26513 , H01L21/26526 , H01L29/7848
摘要： Disclosed herein are various methods of forming stressed silicon-carbon areas in an NMOS transistor device. In one example, a method disclosed herein includes forming a layer of amorphous carbon above a surface of a semiconducting substrate comprising a plurality of N-doped regions and performing an ion implantation process on the layer of amorphous carbon to dislodge carbon atoms from the layer of amorphous carbon and to drive the dislodged carbon atoms into the N-doped regions in the substrate.
摘要翻译： 这里公开了在NMOS晶体管器件中形成应力硅 - 碳区域的各种方法。 在一个实例中，本文公开的方法包括在包括多个N掺杂区域的半导体衬底的表面上方形成无定形碳层，并对无定形碳层进行离子注入工艺以将碳原子从层 并且将移动的碳原子驱动到衬底中的N掺杂区域中。
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12.发明申请Methods of Making Transistor Devices with Elevated Source/Drain Regions to Accommodate Consumption During Metal Silicide Formation Process 有权在金属硅化物形成过程中制造具有升高的源极/排水区域的晶体管器件以容纳消耗的方法公开(公告)号：US20130178034A1
公开(公告)日：2013-07-11
申请号：US13345922
申请日：2012-01-09
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7847 , H01L29/7848
摘要： Disclosed herein are various semiconductor devices with dual metal silicide regions and to various methods of making such devices. One illustrative method disclosed herein includes the steps of forming an upper portion of a source/drain region that is positioned above a surface of a semiconducting substrate, wherein the upper portion of the source/drain region has an upper surface that is positioned above the surface of the substrate by a distance that is at least equal to a target thickness of a metal silicide region to be formed in the upper portion of the source/drain region and forming the metal silicide region in the upper portion of the source/drain region.
摘要翻译： 本文公开了具有双金属硅化物区域的各种半导体器件以及制造这种器件的各种方法。 本文公开的一种说明性方法包括以下步骤：形成位于半导体衬底的表面上方的源极/漏极区的上部，其中源极/漏极区的上部具有位于表面上方的上表面 以至少等于待形成在源/漏区上部的金属硅化物区域的目标厚度的距离，并在源/漏区的上部形成金属硅化物区域。
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13.发明授权Semiconductor device substrate with embedded stress region, and related fabrication methods 有权具有嵌入应力区域的半导体器件基板及相关制造方法公开(公告)号：US08329551B2
公开(公告)日：2012-12-11
申请号：US12947460
申请日：2010-11-16
IPC分类号： H01L21/20
CPC分类号： H01L29/1054 , H01L29/66651
摘要： A semiconductor device substrate is presented here. The semiconductor device substrate includes a layer of first semiconductor material having a first lattice constant, a region of second semiconductor material located in the layer of first semiconductor material, and a layer of epitaxially grown third semiconductor material overlying the layer of first semiconductor material and overlying the region of second semiconductor material. The second semiconductor material has a second lattice constant that is different than the first lattice constant. Moreover, the layer of epitaxially grown third semiconductor material exhibits a stressed zone overlying the region of second semiconductor material. The stressed zone has a third lattice constant that is different than the first lattice constant.
摘要翻译： 这里介绍一种半导体器件基板。 半导体器件衬底包括具有第一晶格常数的第一半导体材料层，位于第一半导体材料层中的第二半导体材料的区域和覆盖在第一半导体材料层上的外延生长的第三半导体材料层 第二半导体材料的区域。 第二半导体材料具有与第一晶格常数不同的第二晶格常数。 此外，外延生长的第三半导体材料层表现出覆盖第二半导体材料区域的应力区域。 应力区具有不同于第一晶格常数的第三晶格常数。
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14.发明授权Complementary stress liner to improve DGO/AVT devices and poly and diffusion resistors 有权互补应力衬垫，用于改善DGO / AVT器件和聚和扩散电阻器公开(公告)号：US08324041B2
公开(公告)日：2012-12-04
申请号：US13023794
申请日：2011-02-09
IPC分类号： H01L21/8238
CPC分类号： H01L28/20 , H01L29/78 , H01L29/7843
摘要： Electron mobility and hole mobility is improved in long channel semiconductor devices and resistors by employing complementary stress liners. Embodiments include forming a long channel semiconductor device on a substrate, and forming a complementary stress liner on the semiconductor device. Embodiments include forming a resistor on a substrate, and tuning the resistance of the resistor by forming a complementary stress liner on the resistor. Compressive stress liners are employed for improving electron mobility in n-type devices, and tensile stress liners are employed for improving hole mobility in p-type devices.
摘要翻译： 通过使用互补应力衬垫，在长沟道半导体器件和电阻器中电子迁移率和空穴迁移率得到改善。 实施例包括在衬底上形成长沟道半导体器件，并在半导体器件上形成互补应力衬垫。 实施例包括在衬底上形成电阻器，并通过在电阻器上形成互补应力衬垫来调节电阻器的电阻。 使用压缩应力衬垫来改善n型器件中的电子迁移率，并且使用拉伸应力衬垫来改善p型器件中的空穴迁移率。
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15.发明申请公开(公告)号：US20120280289A1
公开(公告)日：2012-11-08
申请号：US13101659
申请日：2011-05-05
IPC分类号： H01L29/772 , H01L21/20
CPC分类号： H01L21/02587 , H01L21/02532 , H01L21/02664 , H01L21/28255 , H01L21/823807 , H01L21/84 , H01L29/1054 , H01L29/161 , H01L29/66431 , H01L29/66651 , H01L29/7781 , H01L29/7833
摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming layer of silicon germanium on a P-active region of a semiconducting substrate wherein the layer of silicon germanium has a first concentration of germanium, and performing an oxidation process on the layer of silicon germanium to increase a concentration of germanium in at least a portion of the layer of silicon germanium to a second concentration that is greater than the first concentration of germanium.
摘要翻译： 本文公开了形成半导体器件的方法。 在一个示例中，该方法包括在半导体衬底的P活性区上形成硅锗层，其中硅锗层具有锗的第一浓度，并且在硅锗层上进行氧化处理以增加浓度 在硅锗层的至少一部分中的锗至大于锗的第一浓度的第二浓度。
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公开(公告)号：US20120196422A1
公开(公告)日：2012-08-02
申请号：US13015329
申请日：2011-01-27
IPC分类号： H01L21/336 , H01L21/4763
CPC分类号： H01L29/7845 , H01L21/28518 , H01L21/76829 , H01L21/76837 , H01L29/66545 , H01L29/6656 , H01L29/7843 , H01L29/7847
摘要： Generally, the subject matter disclosed herein relates to sophisticated semiconductor devices and methods for forming the same, wherein a stress memorization technique is used to enhance the performance of MOS transistor elements. One illustrative embodiment includes a method for forming a gate electrode above a channel region of a semiconductor device, wherein the channel region is formed in an active region of a semiconductor substrate. The method further includes forming a dielectric encapsulating layer in direct contact with the gate electrode, and performing a heat treatment process to induce a residual stress in the channel region.
摘要翻译： 通常，本文公开的主题涉及复杂的半导体器件及其形成方法，其中使用应力存储技术来增强MOS晶体管元件的性能。 一个说明性实施例包括在半导体器件的沟道区上方形成栅电极的方法，其中沟道区形成在半导体衬底的有源区中。 该方法还包括形成与栅电极直接接触的电介质封装层，并进行热处理工艺以在沟道区域中引起残余应力。
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17.发明申请Strain Enhancement in Transistors Comprising an Embedded Strain-Inducing Semiconductor Material by Alloy Species Condensation 审中-公开包含嵌入式应变诱导半导体材料的晶体管中的应变增强合金种类冷凝公开(公告)号：US20120161203A1
公开(公告)日：2012-06-28
申请号：US13196318
申请日：2011-08-02
IPC分类号： H01L21/336 , H01L21/225 , H01L29/78 , B82Y99/00 , B82Y40/00
CPC分类号： H01L29/165 , H01L21/18 , H01L29/161 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： In transistors requiring a high compressive strain, the germanium contents may be increased by applying a germanium condensation technique. In some illustrative embodiments, an oxidation process is performed in the presence of a silicon/germanium material obtained on the basis of selective epitaxial growth techniques, thereby increasingly oxidizing the silicon species, while driving the germanium into the lower lying areas of the active region, which finally results in an increased germanium concentration.
摘要翻译： 在需要高压缩应变的晶体管中，可以通过应用锗冷凝技术来增加锗含量。 在一些说明性实施例中，在基于选择性外延生长技术获得的硅/锗材料的存在下进行氧化工艺，从而在将锗驱动到有源区的下部区域的同时越来越多地氧化硅种， 这最终导致锗浓度增加。
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公开(公告)号：US08698243B2
公开(公告)日：2014-04-15
申请号：US13953349
申请日：2013-07-29
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L29/78 , H01L21/26586 , H01L29/1608 , H01L29/165 , H01L29/66636 , H01L29/66659 , H01L29/7848
摘要： Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions.
摘要翻译： 通过引入应变诱导源极 - 漏极区域获得改进的MOSFET器件，其中栅极下方的最接近的“鼻”部分位于与器件表面不同的深度处。 在优选实施例中，间隔开的源极 - 漏极区域可以横向重叠。 这种接近度增加了应变诱导源 - 漏区对源极和漏极之间的感应沟道区域中的载流子迁移率的有利影响。 源极 - 漏极区域通过外部重新填充从栅极的两侧蚀刻的不对称空洞形成。 通过在栅极的仅一个侧壁附近形成初始腔，然后沿着预定的晶体方向蚀刻靠近栅极的两个侧壁的最后的间隔开的源极 - 漏极空腔来获得腔不对称性。 具有不同高度的不同深度和鼻部区域的完成的腔体在栅极下彼此延伸，被外源重新填充用于源极 - 漏极区域的应变诱导半导体材料。
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公开(公告)号：US20130320449A1
公开(公告)日：2013-12-05
申请号：US13482393
申请日：2012-05-29
IPC分类号： H01L21/8238 , H01L27/088 , H01L21/336
CPC分类号： H01L27/0922 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/088 , H01L29/0847 , H01L29/1054 , H01L29/458 , H01L29/4925 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side of each HKMG gate stack, performing halo/extension implants at each side of each HKMG gate stack, forming an oxide liner and nitride spacers on the oxide spacers of each HKMG gate stack, forming deep source/drain regions at opposite sides of the second HKMG gate stack, forming an oxide hardmask over the second HKMG gate stack, forming embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack, and removing the oxide hardmask.
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20.发明申请METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING SUBSTRATE CONTACTS AND INTEGRATED CIRCUITS HAVING SUBSTRATE CONTACTS 有权用于制造具有基板接触的集成电路的方法和具有基板接触的集成电路公开(公告)号：US20130256901A1
公开(公告)日：2013-10-03
申请号：US13436323
申请日：2012-03-30
IPC分类号： H01L21/768 , H01L23/48 , B82Y40/00
CPC分类号： H01L21/76816 , H01L21/28518 , H01L21/743 , H01L21/76802 , H01L2924/0002 , H01L2924/00
摘要： Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contacts are provided. One method includes forming a first trench in a SOI substrate extending through a buried insulating layer to a silicon substrate. A metal silicide region is formed in the silicon substrate exposed by the first trench. A first stress-inducing layer is formed overlying the metal silicide region. A second stress-inducing layer is formed overlying the first stress-inducing layer. An ILD layer of dielectric material is formed overlying the second stress-inducing layer. A second trench is formed extending through the ILD layer and the first and second stress-inducing layers to the metal silicide region. The second trench is filled with a conductive material.
摘要翻译： 提供了具有基板触点的集成电路的制造方法和具有基板触点的集成电路。 一种方法包括在穿过掩埋绝缘层延伸到硅衬底的SOI衬底中形成第一沟槽。 在由第一沟槽暴露的硅衬底中形成金属硅化物区域。 第一应力诱导层形成在金属硅化物区域之上。 第二应力诱导层形成在第一应力诱导层上。 介电材料的ILD层形成在第二应力诱导层上。 形成延伸穿过ILD层和第一和第二应力诱导层到金属硅化物区域的第二沟槽。 第二沟槽填充有导电材料。
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