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    Differential threshold voltage adjustment in PMOS transistors by differential formation of a channel semiconductor material
    5.
    发明授权
    Differential threshold voltage adjustment in PMOS transistors by differential formation of a channel semiconductor material 有权
    通过沟道半导体材料的差分形成，PMOS晶体管中的差分阈值电压调整

    公开(公告)号：US08536009B2

    公开(公告)日：2013-09-17

    申请号：US13197239

    申请日：2011-08-03

    申请人： Peter Javorka ,  Maciej Wiatr ,  Stephan-Detlef Kronholz

    发明人： Peter Javorka ,  Maciej Wiatr ,  Stephan-Detlef Kronholz

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823412 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/82385

    摘要： In sophisticated semiconductor devices, high-k metal gate electrode structures may be provided in an early manufacturing stage wherein the threshold voltage adjustment for P-channel transistors may be accomplished on the basis of a threshold voltage adjusting semiconductor alloy, such as a silicon/germanium alloy, for long channel devices, while short channel devices may be masked during the selective epitaxial growth of the silicon/germanium alloy. In some illustrative embodiments, the threshold voltage adjustment may be accomplished without any halo implantation processes for the P-channel transistors, while the threshold voltage may be tuned by halo implantations for the N-channel transistors.

    摘要翻译： 在复杂的半导体器件中，可以在早期制造阶段提供高k金属栅极电极结构，其中P沟道晶体管的阈值电压调节可以基于阈值电压调节半导体合金（诸如硅/锗） 合金，用于长沟道器件，而在硅/锗合金的选择性外延生长期间可能会掩蔽短沟道器件。 在一些说明性实施例中，阈值电压调整可以在没有用于P沟道晶体管的任何晕圈注入工艺的情况下完成，而阈值电压可以通过N沟道晶体管的晕圈注入来调节。

    Transistor Comprising High-K Metal Gate Electrode Structures Including a Polycrystalline Semiconductor Material and Embedded Strain-Inducing Semiconductor Alloys
    7.
    发明申请
    Transistor Comprising High-K Metal Gate Electrode Structures Including a Polycrystalline Semiconductor Material and Embedded Strain-Inducing Semiconductor Alloys 有权
    晶体管包括包含多晶半导体材料和嵌入式应变诱导半导体合金的高K金属栅电极结构

    公开(公告)号：US20120161250A1

    公开(公告)日：2012-06-28

    申请号：US13198209

    申请日：2011-08-04

    申请人： Stephan-Detlef Kronholz ,  Peter Javorka ,  Maciej Wiatr

    发明人： Stephan-Detlef Kronholz ,  Peter Javorka ,  Maciej Wiatr

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/823807 ,  H01L21/823814

    摘要： When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage on the basis of a silicon/germanium semiconductor alloy for adjusting appropriate electronic conditions in the channel region, the efficiency of a strain-inducing embedded semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by initiating a crystal growth in the silicon material of the gate electrode structure after the gate patterning process. In this manner, the negative strain of the threshold voltage adjusting silicon/germanium alloy may be reduced or compensated for.

    摘要翻译： 当在硅/锗半导体合金的基础上在早期制造阶段形成复杂的高k金属栅极电极结构以调整沟道区域中适当的电子条件时，应变诱导嵌入式半导体合金如硅 /锗合金，可以通过在栅极图案化工艺之后在栅电极结构的硅材料中引发晶体生长来增强。 以这种方式，可以减小或补偿阈值电压调节硅/锗合金的负应变。

    Formation of a channel semiconductor alloy by forming a nitride based hard mask layer
    8.
    发明授权
    Formation of a channel semiconductor alloy by forming a nitride based hard mask layer 有权
    通过形成氮化物基硬掩模层形成沟道半导体合金

    公开(公告)号：US08664066B2

    公开(公告)日：2014-03-04

    申请号：US13552722

    申请日：2012-07-19

    申请人： Rohit Pal ,  Stephan-Detlef Kronholz

    发明人： Rohit Pal ,  Stephan-Detlef Kronholz

    IPC分类号： H01L21/8234

    CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7848 ,  Y02P80/30

    摘要： The present disclosure provides manufacturing techniques in which sophisticated high-k metal gate electrode structures may be formed in an early manufacturing stage on the basis of a selectively applied threshold voltage adjusting semiconductor alloy. In order to reduce the surface topography upon patterning the deposition mask while still allowing the usage of well-established epitaxial growth recipes developed for silicon dioxide-based hard mask materials, a silicon nitride base material may be used in combination with a surface treatment. In this manner, the surface of the silicon nitride material may exhibit a silicon dioxide-like behavior, while the patterning of the hard mask may be accomplished on the basis of highly selective etch techniques.

    摘要翻译： 本公开提供了其中可以在选择性施加的阈值电压调节半导体合金的基础上在早期制造阶段中形成复杂的高k金属栅电极结构的制造技术。 为了在图案化沉积掩模的同时减少表面形貌，同时仍允许使用为基于二氧化硅的硬掩模材料开发的良好的外延生长配方，可以将氮化硅基材与表面处理组合使用。 以这种方式，氮化硅材料的表面可以表现出二氧化硅的行为，而硬掩模的图案化可以基于高选择性蚀刻技术来实现。

    FORMATION OF A CHANNEL SEMICONDUCTOR ALLOY BY FORMING A HARD MASK LAYER STACK AND APPLYING A PLASMA-BASED MASK PATTERNING PROCESS
    9.
    发明申请
    FORMATION OF A CHANNEL SEMICONDUCTOR ALLOY BY FORMING A HARD MASK LAYER STACK AND APPLYING A PLASMA-BASED MASK PATTERNING PROCESS 有权
    通过形成硬掩模层堆叠并应用基于等离子体的掩模图案处理形成通道半导体合金

    公开(公告)号：US20120164805A1

    公开(公告)日：2012-06-28

    申请号：US13238070

    申请日：2011-09-21

    申请人： Stephan-Detlef Kronholz ,  Gunda Beernink ,  Carsten Reichel

    发明人： Stephan-Detlef Kronholz ,  Gunda Beernink ,  Carsten Reichel

    IPC分类号： H01L21/8236 ,  H01L21/336

    CPC分类号： H01L21/823807 ,  H01L21/823828 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/66651

    摘要： When forming sophisticated high-k metal gate electrode structures, a threshold adjusting semiconductor alloy may be formed on the basis of selective epitaxial growth techniques and a hard mask comprising at least two hard mask layers. The hard mask may be patterned on the basis of a plasma-based etch process, thereby providing superior uniformity during the further processing upon depositing the threshold adjusting semiconductor material. In some illustrative embodiments, one hard mask layer is removed prior to actually selectively depositing the threshold adjusting semiconductor material.

    摘要翻译： 当形成复杂的高k金属栅电极结构时，可以基于选择性外延生长技术和包括至少两个硬掩模层的硬掩模形成阈值调节半导体合金。 可以在基于等离子体的蚀刻工艺的基础上对硬掩模进行图案化，从而在沉积阈值调节半导体材料时的进一步处理期间提供优异的均匀性。 在一些说明性实施例中，在实际选择性地沉积阈值调节半导体材料之前去除一个硬掩模层。