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1.发明授权Method of increasing the germanium concentration in a silicon-germanium layer and semiconductor device comprising same 有权增加硅锗层中的锗浓度的方法和包括其的半导体器件的方法公开(公告)号：US08574981B2
公开(公告)日：2013-11-05
申请号：US13101659
申请日：2011-05-05
IPC分类号： H01L21/02
CPC分类号： H01L21/02587 , H01L21/02532 , H01L21/02664 , H01L21/28255 , H01L21/823807 , H01L21/84 , H01L29/1054 , H01L29/161 , H01L29/66431 , H01L29/66651 , H01L29/7781 , H01L29/7833
摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming layer of silicon germanium on a P-active region of a semiconducting substrate wherein the layer of silicon germanium has a first concentration of germanium, and performing an oxidation process on the layer of silicon germanium to increase a concentration of germanium in at least a portion of the layer of silicon germanium to a second concentration that is greater than the first concentration of germanium.
摘要翻译： 本文公开了形成半导体器件的方法。 在一个示例中，该方法包括在半导体衬底的P活性区上形成硅锗层，其中硅锗层具有锗的第一浓度，并且在硅锗层上进行氧化处理以增加浓度 在硅锗层的至少一部分中的锗至大于锗的第一浓度的第二浓度。
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2.发明申请公开(公告)号：US20120280289A1
公开(公告)日：2012-11-08
申请号：US13101659
申请日：2011-05-05
IPC分类号： H01L29/772 , H01L21/20
CPC分类号： H01L21/02587 , H01L21/02532 , H01L21/02664 , H01L21/28255 , H01L21/823807 , H01L21/84 , H01L29/1054 , H01L29/161 , H01L29/66431 , H01L29/66651 , H01L29/7781 , H01L29/7833
摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming layer of silicon germanium on a P-active region of a semiconducting substrate wherein the layer of silicon germanium has a first concentration of germanium, and performing an oxidation process on the layer of silicon germanium to increase a concentration of germanium in at least a portion of the layer of silicon germanium to a second concentration that is greater than the first concentration of germanium.
摘要翻译： 本文公开了形成半导体器件的方法。 在一个示例中，该方法包括在半导体衬底的P活性区上形成硅锗层，其中硅锗层具有锗的第一浓度，并且在硅锗层上进行氧化处理以增加浓度 在硅锗层的至少一部分中的锗至大于锗的第一浓度的第二浓度。
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3.发明授权Methods of making transistor devices with elevated source/drain regions to accommodate consumption during metal silicide formation process 有权制造具有升高的源极/漏极区域的晶体管器件以适应金属硅化物形成过程中的消耗的方法公开(公告)号：US09490344B2
公开(公告)日：2016-11-08
申请号：US13345922
申请日：2012-01-09
IPC分类号： H01L21/02 , H01L21/334 , H01L21/336 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66628 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7847 , H01L29/7848
摘要： Disclosed herein are various semiconductor devices with dual metal silicide regions and to various methods of making such devices. One illustrative method disclosed herein includes the steps of forming an upper portion of a source/drain region that is positioned above a surface of a semiconducting substrate, wherein the upper portion of the source/drain region has an upper surface that is positioned above the surface of the substrate by a distance that is at least equal to a target thickness of a metal silicide region to be formed in the upper portion of the source/drain region and forming the metal silicide region in the upper portion of the source/drain region.
摘要翻译： 本文公开了具有双金属硅化物区域的各种半导体器件以及制造这种器件的各种方法。 本文公开的一种说明性方法包括以下步骤：形成位于半导体衬底的表面上方的源极/漏极区的上部，其中源极/漏极区的上部具有位于表面上方的上表面 以至少等于待形成在源/漏区上部的金属硅化物区域的目标厚度的距离，并在源/漏区的上部形成金属硅化物区域。
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4.发明授权Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations 有权在28nm低功率/高性能技术上的PMOS器件的中间原位掺杂SiGe结，使用硅氧化物封装，早期晕圈和延伸注入公开(公告)号：US08703578B2
公开(公告)日：2014-04-22
申请号：US13482410
申请日：2012-05-29
IPC分类号： H01L21/76
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/0883 , H01L29/0847 , H01L29/1054 , H01L29/1083 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, each including a SiO2 cap, forming extension regions at opposite sides of the first HKMG gate stack, forming a nitride liner and oxide spacers on each side of HKMG gate stack; forming a hardmask over the second HKMG gate stack; forming eSiGe at opposite sides of the first HKMG gate stack, removing the hardmask, forming a conformal liner and nitride spacers on the oxide spacers of each of the first and second HKMG gate stacks, and forming deep source/drain regions at opposite sides of the second HKMG gate stack.
摘要翻译： 提供具有PMOS eSiGe源极/漏极区域的HKMG器件。 实施例包括在衬底上形成第一和第二HKMG栅极堆叠，每个包括SiO 2盖，在第一HKMG栅极堆叠的相对侧形成延伸区域，在HKMG栅极堆叠的每一侧上形成氮化物衬垫和氧化物间隔物; 在第二个HKMG门堆栈上形成硬掩模; 在第一HKMG栅极堆叠的相对侧形成eSiGe，去除硬掩模，在第一和第二HKMG栅极堆叠中的每一个的氧化物间隔物上形成共形衬垫和氮化物间隔物，并且在第二HKMG栅堆叠的相对侧形成深源极/漏极区域 第二个HKMG门栈。
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公开(公告)号：US08524563B2
公开(公告)日：2013-09-03
申请号：US13345457
申请日：2012-01-06
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L21/26586 , H01L29/1608 , H01L29/165 , H01L29/66636 , H01L29/66659 , H01L29/7848
摘要： Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions.
摘要翻译： 通过引入应变诱导源极 - 漏极区域获得改进的MOSFET器件，其中栅极下方的最接近的“鼻”部分位于与器件表面不同的深度处。 在优选实施例中，间隔开的源极 - 漏极区域可以横向重叠。 这种接近度增加了应变诱导源 - 漏区对源极和漏极之间的感应沟道区域中的载流子迁移率的有利影响。 源极 - 漏极区域通过外部重新填充从栅极的两侧蚀刻的不对称空洞形成。 通过在栅极的仅一个侧壁附近形成初始腔，然后沿着预定的晶体方向蚀刻靠近栅极的两个侧壁的最后的间隔开的源极 - 漏极空腔来获得腔不对称性。 具有不同高度的不同深度和鼻部区域的完成的腔体在栅极下彼此延伸，被外源重新填充用于源极 - 漏极区域的应变诱导半导体材料。
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公开(公告)号：US08698243B2
公开(公告)日：2014-04-15
申请号：US13953349
申请日：2013-07-29
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L29/78 , H01L21/26586 , H01L29/1608 , H01L29/165 , H01L29/66636 , H01L29/66659 , H01L29/7848
摘要： Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions.
摘要翻译： 通过引入应变诱导源极 - 漏极区域获得改进的MOSFET器件，其中栅极下方的最接近的“鼻”部分位于与器件表面不同的深度处。 在优选实施例中，间隔开的源极 - 漏极区域可以横向重叠。 这种接近度增加了应变诱导源 - 漏区对源极和漏极之间的感应沟道区域中的载流子迁移率的有利影响。 源极 - 漏极区域通过外部重新填充从栅极的两侧蚀刻的不对称空洞形成。 通过在栅极的仅一个侧壁附近形成初始腔，然后沿着预定的晶体方向蚀刻靠近栅极的两个侧壁的最后的间隔开的源极 - 漏极空腔来获得腔不对称性。 具有不同高度的不同深度和鼻部区域的完成的腔体在栅极下彼此延伸，被外源重新填充用于源极 - 漏极区域的应变诱导半导体材料。
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公开(公告)号：US20130320449A1
公开(公告)日：2013-12-05
申请号：US13482393
申请日：2012-05-29
IPC分类号： H01L21/8238 , H01L27/088 , H01L21/336
CPC分类号： H01L27/0922 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/088 , H01L29/0847 , H01L29/1054 , H01L29/458 , H01L29/4925 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side of each HKMG gate stack, performing halo/extension implants at each side of each HKMG gate stack, forming an oxide liner and nitride spacers on the oxide spacers of each HKMG gate stack, forming deep source/drain regions at opposite sides of the second HKMG gate stack, forming an oxide hardmask over the second HKMG gate stack, forming embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack, and removing the oxide hardmask.
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8.发明申请METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING SUBSTRATE CONTACTS AND INTEGRATED CIRCUITS HAVING SUBSTRATE CONTACTS 有权用于制造具有基板接触的集成电路的方法和具有基板接触的集成电路公开(公告)号：US20130256901A1
公开(公告)日：2013-10-03
申请号：US13436323
申请日：2012-03-30
IPC分类号： H01L21/768 , H01L23/48 , B82Y40/00
CPC分类号： H01L21/76816 , H01L21/28518 , H01L21/743 , H01L21/76802 , H01L2924/0002 , H01L2924/00
摘要： Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contacts are provided. One method includes forming a first trench in a SOI substrate extending through a buried insulating layer to a silicon substrate. A metal silicide region is formed in the silicon substrate exposed by the first trench. A first stress-inducing layer is formed overlying the metal silicide region. A second stress-inducing layer is formed overlying the first stress-inducing layer. An ILD layer of dielectric material is formed overlying the second stress-inducing layer. A second trench is formed extending through the ILD layer and the first and second stress-inducing layers to the metal silicide region. The second trench is filled with a conductive material.
摘要翻译： 提供了具有基板触点的集成电路的制造方法和具有基板触点的集成电路。 一种方法包括在穿过掩埋绝缘层延伸到硅衬底的SOI衬底中形成第一沟槽。 在由第一沟槽暴露的硅衬底中形成金属硅化物区域。 第一应力诱导层形成在金属硅化物区域之上。 第二应力诱导层形成在第一应力诱导层上。 介电材料的ILD层形成在第二应力诱导层上。 形成延伸穿过ILD层和第一和第二应力诱导层到金属硅化物区域的第二沟槽。 第二沟槽填充有导电材料。
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9.发明申请COMPLEMENTARY STRESS LINER TO IMPROVE DGO/AVT DEVICES AND POLY AND DIFFUSION RESISTORS 有权补充应力衬管改善DGO / AVT器件和聚偏振电阻公开(公告)号：US20120199912A1
公开(公告)日：2012-08-09
申请号：US13023794
申请日：2011-02-09
CPC分类号： H01L28/20 , H01L29/78 , H01L29/7843
摘要： Electron mobility and hole mobility is improved in long channel semiconductor devices and resistors by employing complementary stress liners. Embodiments include forming a long channel semiconductor device on a substrate, and forming a complementary stress liner on the semiconductor device. Embodiments include forming a resistor on a substrate, and tuning the resistance of the resistor by forming a complementary stress liner on the resistor. Compressive stress liners are employed for improving electron mobility in n-type devices, and tensile stress liners are employed for improving hole mobility in p-type devices.
摘要翻译： 通过使用互补应力衬垫，在长沟道半导体器件和电阻器中电子迁移率和空穴迁移率得到改善。 实施例包括在衬底上形成长沟道半导体器件，并在半导体器件上形成互补应力衬垫。 实施例包括在衬底上形成电阻器，并通过在电阻器上形成互补应力衬垫来调谐电阻器的电阻。 使用压缩应力衬垫来改善n型器件中的电子迁移率，并且使用拉伸应力衬垫来改善p型器件中的空穴迁移率。
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10.发明申请Transistor Comprising an Embedded Sigma Shaped Sequentially Formed Semiconductor Alloy 有权晶体管包括嵌入式西格玛形成的顺序形成的半导体合金公开(公告)号：US20120161204A1
公开(公告)日：2012-06-28
申请号：US13232571
申请日：2011-09-14
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： In sophisticated transistors, a specifically designed semiconductor material, such as a strain-inducing semiconductor material, may be sequentially provided in the drain region and the source region, thereby enabling a significant degree of lateral extension of the grown semiconductor materials without jeopardizing mechanical integrity of the transistor during the processing thereof. For example, semiconductor devices having different drain and source sides may be provided on the basis of sequentially provided embedded semiconductor materials.
摘要翻译： 在复杂的晶体管中，可以在漏极区域和源极区域中顺序提供诸如应变诱导半导体材料的特殊设计的半导体材料，从而使得生长的半导体材料的显着程度的横向延伸，而不会危害机械完整性 晶体管在其处理期间。 例如，可以在依次提供的嵌入式半导体材料的基础上提供具有不同漏极和源极侧的半导体器件。
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