公开(公告)号：US07960732B2

公开(公告)日：2011-06-14

申请号：US12082495

申请日：2008-04-11

申请人： Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

发明人： Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

IPC分类号： H01L29/04

CPC分类号： H01L27/12 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2001/13629 ,  H01L27/124 ,  H01L27/1288

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在所述下导电膜的第一部分上形成像素电极; 去除下导电膜的第二部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

公开(公告)号：US20080191212A1

公开(公告)日：2008-08-14

申请号：US12082495

申请日：2008-04-11

申请人： Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

发明人： Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

IPC分类号： H01L29/04

CPC分类号： H01L27/12 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2001/13629 ,  H01L27/124 ,  H01L27/1288

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在所述下导电膜的第一部分上形成像素电极; 去除下导电膜的第二部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

公开(公告)号：US20060172472A1

公开(公告)日：2006-08-03

申请号：US11395434

申请日：2006-03-30

申请人： Jeong-Young Lee ,  Se-Hwam Yu ,  Sang-Jin Jeon ,  Min-Wook Park

发明人： Jeong-Young Lee ,  Se-Hwam Yu ,  Sang-Jin Jeon ,  Min-Wook Park

IPC分类号： H01L29/04 ,  H01L21/84

CPC分类号： H01L27/12 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2001/13629 ,  H01L27/124 ,  H01L27/1288

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在所述下导电膜的第一部分上形成像素电极; 去除下导电膜的第二部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

公开(公告)号：US20050082535A1

公开(公告)日：2005-04-21

申请号：US10926719

申请日：2004-08-26

申请人： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

发明人： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

IPC分类号： G02F1/136 ,  G02F1/133 ,  G02F1/1339 ,  G02F1/1368 ,  G03C1/85 ,  G03C5/00 ,  G09F9/30 ,  H01L21/00 ,  H01L21/336 ,  H01L29/786

CPC分类号： G02F1/1368 ,  G02F1/1339

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在下导电膜的第一和第二部分上形成像素电极和一对冗余电极，所述冗余电极暴露下导电膜的第二部分的一部分; 去除下导电膜的第二部分的暴露部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

公开(公告)号：US20050030440A1

公开(公告)日：2005-02-10

申请号：US10884083

申请日：2004-07-01

申请人： Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

发明人： Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

IPC分类号： G02F1/13 ,  G02F1/1339 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/30 ,  H01L21/28 ,  H01L21/3205 ,  H01L23/52 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  G02F1/136

CPC分类号： H01L27/12 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2001/13629 ,  H01L27/124 ,  H01L27/1288

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在所述下导电膜的第一部分上形成像素电极; 去除下导电膜的第二部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

公开(公告)号：US07459323B2

公开(公告)日：2008-12-02

申请号：US11512805

申请日：2006-08-30

申请人： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

发明人： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

IPC分类号： H01L21/00

CPC分类号： G02F1/1368 ,  G02F1/1339

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在下导电膜的第一和第二部分上形成像素电极和一对冗余电极，所述冗余电极暴露下导电膜的第二部分的一部分; 去除下导电膜的第二部分的暴露部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

公开(公告)号：US20140309387A1

公开(公告)日：2014-10-16

申请号：US14112849

申请日：2012-08-24

申请人： Won-Hee Kim ,  Kyung-Seop Noh ,  Nan-Young Lee ,  Sang-Jin Jeon

发明人： Won-Hee Kim ,  Kyung-Seop Noh ,  Nan-Young Lee ,  Sang-Jin Jeon

IPC分类号： C08F4/76

CPC分类号： C08F4/76 ,  B01J21/06 ,  C08F4/64 ,  C08F4/659 ,  C08F10/00 ,  C08F4/64141 ,  C08F4/65908 ,  C08F210/16 ,  C08F210/14 ,  C08F2500/03

摘要： The present invention relates to a transition metal catalyst composition which can exhibit high reactivity in a polymerization reaction of a polyolefin and can easily control characteristics such as chemical structure, molecular weight distribution, mechanical properties, and the like of a synthesized polyolefin, and a method of preparing a polyolefin using the catalyst composition.

摘要翻译： 本发明涉及能够在聚烯烃的聚合反应中表现出高反应性的过渡金属催化剂组合物，并且可以容易地控制合成聚烯烃的化学结构，分子量分布，机械性能等特性，以及方法 使用该催化剂组合物制备聚烯烃。

公开(公告)号：US07288955B2

公开(公告)日：2007-10-30

申请号：US11217591

申请日：2005-08-31

申请人： Sang-Jin Jeon

发明人： Sang-Jin Jeon

IPC分类号： G01R31/00

CPC分类号： G09G3/006

摘要： A panel for a display device includes a display area and a peripheral area. The display area comprises a plurality of pixels each comprising a switching element and gate lines and data lines connected to the pixels. The peripheral area comprises a plurality of gate driving integrated circuit regions, a plurality of data driving integrated circuit regions, a plurality of repair lines disposed along the edge of the panel, connecting pads connected to both ends of the repair lines, a test line connected to at least one connecting pad, and a test pad connected to the test line. A test method for detecting disconnection of the data lines is also provided.

摘要翻译： 用于显示装置的面板包括显示区域和外围区域。 显示区域包括多个像素，每个像素包括开关元件和连接到像素的栅极线和数据线。 外围区域包括多个栅极驱动集成电路区域，多个数据驱动集成电路区域，沿着面板边缘设置的多个修复线，连接到修复线两端的连接焊盘，连接的测试线 至少一个连接焊盘和连接到测试线的测试焊盘。 还提供了用于检测数据线断开的测试方法。

公开(公告)号：US08797491B2

公开(公告)日：2014-08-05

申请号：US12698404

申请日：2010-02-02

申请人： Jeong-Il Kim ,  Yun-Hee Kwak ,  Sang-Jin Jeon

发明人： Jeong-Il Kim ,  Yun-Hee Kwak ,  Sang-Jin Jeon

IPC分类号： G02F1/1345

CPC分类号： G02F1/1345 ,  G02F1/136286

摘要： A display device may include an insulating substrate, a pixel electrode formed on the insulating substrate, a circuit board connected to the insulating substrate, a first wiring connected to the circuit board, and a second wiring for transmitting a signal to the pixel electrode. The second wiring may be connected to the first wiring, and the second wiring may have a larger resistance than the first wiring. Portions of the first wiring or the second wiring may include a zigzag pattern, and a swing width of a zigzag pattern of the second wiring may be varied depending on the position of the second wiring.

摘要翻译： 显示装置可以包括绝缘基板，形成在绝缘基板上的像素电极，连接到绝缘基板的电路板，连接到电路板的第一布线和用于将信号传输到像素电极的第二布线。 第二布线可以连接到第一布线，并且第二布线可以具有比第一布线更大的电阻。 第一布线或第二布线的部分可以包括锯齿形图案，并且第二布线的之字形图案的摆动宽度可以根据第二布线的位置而变化。

公开(公告)号：US20130303704A1

公开(公告)日：2013-11-14

申请号：US13980869

申请日：2012-01-19

申请人： Sang-Jin Jeon ,  Seung-Ki Park ,  Kyung-Seop Noh ,  Nan-Young Lee ,  Won-Hee Kim ,  Sang-Eun An

发明人： Sang-Jin Jeon ,  Seung-Ki Park ,  Kyung-Seop Noh ,  Nan-Young Lee ,  Won-Hee Kim ,  Sang-Eun An

IPC分类号： C08F295/00

CPC分类号： C08F295/00 ,  C08F210/16 ,  C08F297/08 ,  C08F301/00 ,  C08F2500/10 ,  C08J5/18 ,  C08J2323/16

摘要： The present description relates to an olefin block copolymer preferably useful to form nonslip pads due to excellences in elasticity and heat resistance, and a sheet-shaped molded body comprising the olefin block copolymer The olefin block copolymer includes a plurality of blocks or segments, each of which includes an ethylene or propylene repeating unit and an α-olefin repeating unit at different weight fractions. The olefin block copolymer satisfies a defined relationship when a load of 5 to 10 kg is applied to a sheet-shaped molded body of the block copolymer for 12 hours or longer at a temperature of 60° C. or higher, and then removed.

摘要翻译： 本发明涉及由于弹性和耐热性优异而优选用于形成非滑垫的烯烃嵌段共聚物和包含烯烃嵌段共聚物的片状成型体。烯烃嵌段共聚物包括多个嵌段或链段 其包括不同重量分数的乙烯或丙烯重复单元和α-烯烃重复单元。 当在60℃以上的温度下对嵌段共聚物的片状成型体施加5〜10kg的负荷12小时以上时，烯烃嵌段共聚物满足规定的关系，然后除去。