公开(公告)号：US20170124968A1

公开(公告)日：2017-05-04

申请号：US15333899

申请日：2016-10-25

Applicant: Japan Display Inc.

Inventor： Takehiro SHIMA ,  Takayuki NAKAO

IPC: G09G3/36 ,  G02F1/1335 ,  G02F1/1362 ,  G02F1/1343

CPC classification number: G09G3/3614 ,  G02F1/133512 ,  G02F1/133553 ,  G02F1/134309 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134345 ,  G02F2201/121 ,  G02F2201/123 ,  G09G3/3611 ,  G09G3/3677 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2300/0426 ,  G09G2300/0452 ,  G09G2300/0857 ,  G09G2310/08 ,  G09G2320/0271

Abstract: According to one embodiment, a display device includes a pixel electrode and a memory in each of pixels, a common electrode, a first drive circuit which supplies a digital signal, a second drive circuit which supplies an AC common signal to the common electrode, a storage control circuit which stores the digital signal in the memory in a storage period, and a select control circuit which selectively supplies, in a display period, to the pixel electrode, one of a display signal and a non-display signal. A frequency of the common signal in the storage period is a first frequency. The frequency of the common signal in the display period is a second frequency. The first frequency is higher than the second frequency.

公开(公告)号：US20230176428A1

公开(公告)日：2023-06-08

申请号：US18074074

申请日：2022-12-02

Applicant: Japan Display Inc.

Inventor： Takayuki NAKAO ,  Takehiro SHIMA

IPC: G02F1/1343 ,  G02F1/1335 ,  G02F1/1362

CPC classification number: G02F1/134309 ,  G02F1/133553 ,  G02F1/133514 ,  G02F1/136227 ,  G02F1/136286

Abstract: According to an aspect, a display device includes: an array substrate including pixels arrayed in a first direction and a second direction, each pixel including a reflective electrode and a light-transmitting electrode, the light-transmitting electrode partially overlapping the reflective electrode when viewed in the third direction orthogonal to the first direction and the second direction; a counter substrate including a common electrode overlapping the reflective electrodes and a color filter including a plurality of colors; and a backlight facing the counter substrate with the array substrate therebetween. The color filter is configured such that different colors are adjacently arranged in a first direction and each color extends in a second direction. Part of one of the light-transmitting electrodes protrudes between two of the reflective electrodes adjacently disposed in the second direction.

公开(公告)号：US20190005904A1

公开(公告)日：2019-01-03

申请号：US16020055

申请日：2018-06-27

Applicant: Japan Display Inc.

Inventor： Yutaka MITSUZAWA ,  Takayuki NAKAO ,  Yutaka OZAWA ,  Masaya TAMAKI

IPC: G09G3/36

Abstract: A display device includes: a plurality of sub-pixels each including a memory block; a clock signal output circuit configured to output a plurality of clock signals having different frequencies; a selection circuit configured to select one of the clock signals as a selected clock signal; a plurality of memory selection line groups provided for respective rows; a memory selection circuit configured to output a memory selection signal concurrently to the memory selection line groups in synchronization with the selected clock signal, the memory selection signal being a signal for selecting one from a plurality of memories in each of the memory blocks; a common electrode to which a common potential common to the sub-pixels is supplied; and a common-electrode driving circuit configured to switch the common potential in synchronization with the reference clock signal and output the switched common potential.

公开(公告)号：US20180075823A1

公开(公告)日：2018-03-15

申请号：US15699634

申请日：2017-09-08

Applicant: Japan Display Inc.

Inventor： Takayuki NAKAO ,  Takehiro SHIMA

IPC: G09G5/395 ,  G09G3/36 ,  G09G5/393

CPC classification number: G09G5/395 ,  G09G3/3655 ,  G09G3/3677 ,  G09G5/393 ,  G09G2300/0857 ,  G09G2310/08 ,  G09G2330/026

Abstract: According to an aspect, a display apparatus includes: a plurality of pixels each of which includes a memory for storing a signal; a plurality of image signal lines each of which is configured to supply the signal; a plurality of switches each of which is included in a corresponding one of the pixels and couples a corresponding one of the image signal lines to the memory of the corresponding one of the pixels; a plurality of gate signal lines; a plurality of logic circuits coupled in series, the logic circuit at a most upstream stage being configured to receive a control signal, and each of the logic circuits being configured to output an output signal; and a plurality of control circuits each of which is configured to output a gate signal to a corresponding one of the gate signal lines based on the control signal or the output signal.

公开(公告)号：US20170200407A1

公开(公告)日：2017-07-13

申请号：US15405616

申请日：2017-01-13

Applicant: Japan Display Inc.

Inventor： Takayuki NAKAO ,  Takehiro SHIMA

IPC: G09G3/20

CPC classification number: G09G3/2074 ,  G09G3/2003 ,  G09G3/2092 ,  G09G3/3614 ,  G09G3/3648 ,  G09G3/3688 ,  G09G2300/0439 ,  G09G2300/0452 ,  G09G2300/0857 ,  G09G2320/0666

Abstract: According to an embodiment, in a display device, pixels have memories respectively. A signal supply circuit includes a mode control circuit, and switches into a first mode or a second mode to supply digital data pieces to sub-pixels. In the first mode, the circuit receives from the outside first video data pieces corresponding to n sub-pixels, and supplies digital data pieces for the n sub-pixels to corresponding memories. In the second mode, the signal supply circuit receives from the outside second video data pieces corresponding to m sub-pixels fewer than n sub-pixels, and supplies digital data pieces for the n sub-pixels to corresponding memories based on the second video data pieces.