公开(公告)号：US20130207250A1

公开(公告)日：2013-08-15

申请号：US13396207

申请日：2012-02-14

申请人： Martin Eckert ,  Otto Torreiter ,  Quintino L. Trianni

发明人： Martin Eckert ,  Otto Torreiter ,  Quintino L. Trianni

IPC分类号： H01L23/495 ,  H01L21/58

CPC分类号： H01L24/75 ,  G01R1/0466 ,  G01R1/0483 ,  H01L21/4853 ,  H01L21/67144 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/75252 ,  H01L2224/75301 ,  H01L2224/75315 ,  H01L2224/75316 ,  H01L2224/75501 ,  H01L2224/757 ,  H01L2224/75754 ,  H01L2224/75756 ,  H01L2224/759 ,  H01L2224/81121 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/81908 ,  H05K13/0413 ,  Y10T29/53178 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012

摘要： A chip attach frame is used to align pins of an integrated circuit chip with pads on a chip carrier. A frame block has a socket defining two alignment edges that form a reference corner. The chip is lowered into the socket, and the chip carrier is inclined while it supports the frame block and chip until the chip moves under force of gravity to the reference corner. Once located at the reference corner, the chip position is carefully adjusted by moving the frame block in the x- and y-directions until the pins are aligned with the pads. The frame block is spring biased against movement in the x- and y-directions, and the position of the frame block is adjusted using thumbscrews. A plunger mechanism can be used to secure the integrated circuit chip in forcible engagement with the chip carrier once the pins are aligned with the pads.

公开(公告)号：US07921388B2

公开(公告)日：2011-04-05

申请号：US11847759

申请日：2007-08-30

申请人： Sebastian Ehrenreich ,  Juergen Pille ,  Otto Torreiter

发明人： Sebastian Ehrenreich ,  Juergen Pille ,  Otto Torreiter

IPC分类号： G06F17/50 ,  G11C16/06

CPC分类号： G11C5/145 ,  G11C8/08 ,  G11C11/413

摘要： The invention relates to a wordline booster circuit, especially an SRAM-wordline booster circuit, comprising a driving element (20) for shifting a voltage level of a charge storage element (50) for storing a charge necessary to generate a boosted voltage (Vb), a feedback element (30) for controlling the switching state of a charging element (40), wherein the charging element (40) is actively switchable between a turned-off state during a first time interval and a turned-on state during a second time interval, and an output port (14) for supplying the boost voltage to at least one wordline-driver circuit (100) of a memory device (200). The invention relates also to an operation method for such a wordline booster circuit as well as a memory array implementation on an integrated circuit, especially an SRAM memory array, with a wordline booster circuit.

摘要翻译： 本发明涉及一种字线升压电路，特别是一种SRAM字线升压电路，它包括用于移动电荷存储元件（50）的电压电平的驱动元件（20），用于存储产生升压电压（Vb）所需的电荷， ，用于控制充电元件（40）的开关状态的反馈元件（30），其中所述充电元件（40）可在第一时间间隔期间的关断状态和第二时间间隔期间的接通状态之间主动切换 以及用于将升压电压提供给存储装置（200）的至少一个字线驱动电路（100）的输出端口（14）。 本发明还涉及这种字线升压电路的操作方法以及具有字线升压电路的集成电路，特别是SRAM存储器阵列上的存储器阵列实现。

公开(公告)号：US20080068901A1

公开(公告)日：2008-03-20

申请号：US11847754

申请日：2007-08-30

申请人： Sebastian Ehrenreich ,  Juergen Pille ,  Otto Torreiter

发明人： Sebastian Ehrenreich ,  Juergen Pille ,  Otto Torreiter

IPC分类号： G11C7/00

CPC分类号： G11C5/145 ,  G11C8/08 ,  G11C11/413

摘要： The invention relates to a wordline booster circuit, especially an SRAM-wordline booster circuit, comprising a driving element (20) for shifting a voltage level of a charge storage element (50) for storing a charge necessary to generate a boosted voltage (Vb), a feedback element (30) for controlling the switching state of a charging element (40), wherein the charging element (40) is actively switchable between a turned-off state during a first time interval and a turned-on state during a second time interval, and an output port (14) for supplying the boost voltage to at least one wordline-driver circuit (100) of a memory device (200). The invention relates also to an operation method for such a wordline booster circuit as well as a memory array implementation on an integrated circuit, especially an SRAM memory array, with a wordline booster circuit.

摘要翻译： 本发明涉及一种字线升压电路，特别是一种SRAM字线升压电路，它包括用于移动电荷存储元件（50）的电压电平的驱动元件（20），用于存储产生升压电压（Vb）所需的电荷， ，用于控制充电元件（40）的开关状态的反馈元件（30），其中所述充电元件（40）可在第一时间间隔期间的关断状态和第二时间间隔期间的接通状态之间主动切换 以及用于将升压电压提供给存储装置（200）的至少一个字线驱动电路（100）的输出端口（14）。 本发明还涉及这种字线升压电路的操作方法以及具有字线升压电路的集成电路，特别是SRAM存储器阵列上的存储器阵列实现。

公开(公告)号：US06127254A

公开(公告)日：2000-10-03

申请号：US189427

申请日：1998-11-10

申请人： Ulrich Diebold ,  Otto Torreiter ,  Hans Wiedemann

发明人： Ulrich Diebold ,  Otto Torreiter ,  Hans Wiedemann

IPC分类号： G01R31/28 ,  H01L21/60 ,  H01L21/68 ,  H01L21/44

CPC分类号： H01L24/81 ,  G01R31/2887 ,  H01L21/68 ,  H01L2224/10165 ,  H01L2224/8014 ,  H01L2224/81136 ,  H01L2224/8114 ,  H01L2224/81801 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014

摘要： A method and device are presented for precise alignment of a semiconductor chip on a substrate which, in a simple and cost-effective way, permit accurate alignment of individual chips on a substrate to be ensured.

摘要翻译： 提出了一种方法和装置，用于在基板上精确对准半导体芯片，其以简单且成本有效的方式允许确保衬底上的各个芯片的精确对准。

公开(公告)号：US5742616A

公开(公告)日：1998-04-21

申请号：US486468

申请日：1995-06-07

申请人： Otto Torreiter ,  Roland Metzger ,  Dieter Wendel

发明人： Otto Torreiter ,  Roland Metzger ,  Dieter Wendel

IPC分类号： G06F11/10 ,  G06F12/14 ,  G06F12/16 ,  G06F15/78 ,  G06F21/00 ,  G06F21/24 ,  G11C29/40 ,  G11C29/44 ,  G01R31/28

CPC分类号： G06F21/79 ,  G06F12/1466 ,  G06F21/64 ,  G11C29/40 ,  G11C29/44 ,  G06F11/1004

摘要： A self test circuit provides a general statement about the condition of a coupled memory which indicates whether a wanted or unwanted manipulation or alteration of the memory has occurred. The contents of the memory are not derivable from the general statement. The general statement is preferably a "fail" or "pass" statement stating whether a deviation in the contents of the memory with respect to a last executed test has been detected or not. The testing of a non-volatile memory is executed by generating a signature from the contents of the non-volatile memory and comparing the generated signature with a reference value of the signature. When the comparison of the generated signature with the reference value indicates a different, a signal is issued and access to the non-volatile memory is restricted and/or a failure procedure is started. Access to the non-volatile memory is allowed when the comparison signature with the reference value indicates no difference. In order to allow a test of whether an alteration of the contents of the non-volatile memory has happened between successive authorized applications, a new signature from the contents of the non-volatile memory is generated after each application and stored as a new reference value.

摘要翻译： 自检电路提供关于耦合存储器的状况的一般说明，其指示是否发生了想要的或不需要的操作或改变存储器。 内存的内容不能从一般语句中推导出来。 一般性声明优选地是“失败”或“通过”声明，说明是否已经检测到相对于最后执行的测试的存储器的内容的偏差。 通过从非易失性存储器的内容生成签名并将生成的签名与签名的参考值进行比较来执行非易失性存储器的测试。 当生成的签名与参考值的比较指示不同时，发出信号并且限制访问非易失性存储器和/或启动故障过程。 当与参考值的比较签名没有差异时，允许访问非易失性存储器。 为了允许在连续授权的应用程序之间发生非易失性存储器的内容的改变的测试，在每个应用程序之后生成来自非易失性存储器的内容的新签名，并将其存储为新的参考值 。