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公开(公告)号：US20080203492A1
公开(公告)日：2008-08-28
申请号：US12117371
申请日：2008-05-08
申请人： Ethan Harrison Cannon , Toshiharu Furukawa , Mark Charles Hakey , David Vaclav Horak , Charles William Koburger , Jimmy Konstantinos Kontos , Jack Allan Mandelman , William Robert Tonti
发明人： Ethan Harrison Cannon , Toshiharu Furukawa , Mark Charles Hakey , David Vaclav Horak , Charles William Koburger , Jimmy Konstantinos Kontos , Jack Allan Mandelman , William Robert Tonti
IPC分类号： H01L27/092
CPC分类号： H01L27/0921 , H01L21/76229 , H01L21/823878
摘要： Semiconductor methods and device structures for suppressing latch-up in bulk CMOS devices. The method comprises forming a trench in the semiconductor material of the substrate with first sidewalls disposed between a pair of doped wells, also defined in the semiconductor material of the substrate. The method further comprises forming an etch mask in the trench to partially mask the base of the trench, followed by removing the semiconductor material of the substrate exposed across the partially masked base to define narrowed second sidewalls that deepen the trench. The deepened trench is filled with a dielectric material to define a trench isolation region for devices built in the doped wells. The dielectric material filling the deepened extension of the trench enhances latch-up suppression.
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公开(公告)号：US20080144348A1
公开(公告)日：2008-06-19
申请号：US11612809
申请日：2006-12-19
申请人： Ethan Harrison Cannon , Toshiharu Furukawa , David Vaclav Horak , Charles William Koburger , Jack A. Mandelman
发明人： Ethan Harrison Cannon , Toshiharu Furukawa , David Vaclav Horak , Charles William Koburger , Jack A. Mandelman
IPC分类号： G11C5/06
CPC分类号： G11C11/4125
摘要： An SRAM cell. The SRAM cell includes a first CMOS inverter and a second CMOS inverter, an input of the first inverter connected to an output of the second inverter and an input of the second inverter connected to an output of the first inverter, a first MOSFET interposed between an output of the first CMOS inverter and a first plate of a first capacitor, a second plate of the first capacitor connected to a high voltage terminal of a power supply; a second MOSFET interposed between an output of the second CMOS inverter and a first plate of a second capacitor, a second plate of the second capacitor connected to the high voltage terminal of the power supply; and a control signal line connected to a gate of the first MOSFET and a gate of the second MOSFET.
摘要翻译： 一个SRAM单元。 SRAM单元包括第一CMOS反相器和第二CMOS反相器，连接到第二反相器的输出的第一反相器的输入和连接到第一反相器的输出的第二反相器的输入， 第一CMOS反相器的输出和第一电容器的第一板，第一电容器的第二板连接到电源的高电压端子; 插入在所述第二CMOS反相器的输出端和第二电容器的第一板之间的第二MOSFET，所述第二电容器的第二板连接到所述电源的高电压端子; 以及连接到第一MOSFET的栅极和第二MOSFET的栅极的控制信号线。
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13.发明申请公开(公告)号：US20080128629A1
公开(公告)日：2008-06-05
申请号：US12028850
申请日：2008-02-11
IPC分类号： G01T1/02
CPC分类号： G01T1/244
摘要： A method, device and system for monitoring ionizing radiation. The method including: collecting an ionizing radiation induced charge collected by the depletion region of a diode formed in a silicon layer below an oxide layer buried below a surface of a silicon substrate; and coupling a cathode of the diode to a precharged node of a clocked logic circuit such that the ionizing radiation induced charge collected by a depletion region of the diode will discharge the precharged node and change an output state of the clocked logic circuit.
摘要翻译： 一种用于监测电离辐射的方法，装置和系统。 该方法包括：收集由埋在硅衬底表面下方的氧化物层下面的硅层中形成的二极管的耗尽区收集的电离辐射感应电荷; 以及将二极管的阴极耦合到时钟逻辑电路的预充电节点，使得由二极管的耗尽区收集的电离辐射感应电荷将放电预充电节点并改变时钟逻辑电路的输出状态。
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14.发明授权Neutralization of trapped charge in a charge accumulation layer of a semiconductor structure 有权俘获电荷在半导体结构的电荷累积层中的中和公开(公告)号：US08035200B2
公开(公告)日：2011-10-11
申请号：US12792837
申请日：2010-06-03
IPC分类号： H01L29/786 , H01L23/62 , H01L23/58 , H01L27/12
CPC分类号： H01L21/743 , H01L21/76275
摘要： A semiconductor structure. The semiconductor structure includes a semiconductor layer, a charge accumulation layer on top of the semiconductor layer, a doped region in direct physical contact with the semiconductor layer; and a device layer on and in direct physical contact with the charge accumulation layer. The charge accumulation layer includes trapped charges of a first sign. The doped region and the semiconductor layer forms a P−N junction diode. The P−N junction diode includes free charges of a second sign opposite to the first sign. The trapped charge in the charge accumulation layer exceeds a preset limit above which semiconductor structure is configured to malfunction. A first voltage is applied to the doped region. A second voltage is applied to the semiconductor layer. A third voltage is applied to the device layer. The third voltage exceeds the first voltage and the second voltage.
摘要翻译： 半导体结构。 半导体结构包括半导体层，在半导体层顶部的电荷累积层，与半导体层直接物理接触的掺杂区域; 以及与电荷累积层直接物理接触的器件层。 电荷累积层包括第一符号的俘获电荷。 掺杂区域和半导体层形成P-N结二极管。 P-N结二极管包括与第一个符号相反的第二个符号的免费电荷。 电荷累积层中的俘获电荷超过预设极限，超过该限制，半导体结构被配置为故障。 第一电压被施加到掺杂区域。 向半导体层施加第二电压。 第三电压被施加到器件层。 第三电压超过第一电压和第二电压。
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公开(公告)号：US07750406B2
公开(公告)日：2010-07-06
申请号：US11877871
申请日：2007-10-24
申请人： Ethan Harrison Cannon , Toshiharu Furukawa , John Gerard Gaudiello , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Jack Allan Mandelman , William Robert Tonti
发明人： Ethan Harrison Cannon , Toshiharu Furukawa , John Gerard Gaudiello , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Jack Allan Mandelman , William Robert Tonti
CPC分类号： H01L21/76264
摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes devices formed in a hybrid substrate characterized by semiconductor islands of different crystal orientations. An insulating layer divides the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.
摘要翻译： 设计结构体现在机器可读介质中，用于设计，制造或测试设计，其中设计结构包括以混合衬底形成的器件，其特征在于具有不同晶体取向的半导体岛。 绝缘层将至少一个不同晶体取向的岛分成相互排列的器件和体区。 身体区域可以相对于装置区域电浮动。
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16.发明授权Device for monitoring ionizing radiation in silicon-on insulator integrated circuits 有权用于监控绝缘体上硅集成电路中的电离辐射的装置公开(公告)号：US07473904B2
公开(公告)日：2009-01-06
申请号：US12028850
申请日：2008-02-11
IPC分类号： H01L31/00
CPC分类号： G01T1/244
摘要： A device and system for monitoring ionizing radiation. The device including: a diode formed in a silicon layer below an oxide layer buried below a surface of a silicon substrate; and a cathode of the diode coupled to a precharged node of a clocked logic circuit, an output state of the clocked logic circuit responsive a change in state of the precharged node, a state of the precharged node responsive to ionizing radiation induced charge collected by a depletion region of the diode and collected in the cathode.
摘要翻译： 用于监测电离辐射的装置和系统。 该器件包括：二极管，其形成在埋在硅衬底的表面下方的氧化物层下方的硅层中; 并且二极管的阴极耦合到时钟逻辑电路的预充电节点，时钟逻辑电路的输出状态响应于预充电节点的状态改变，预充电节点的状态响应于电离辐射诱发的电荷 二极管的耗尽区域并收集在阴极中。
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17.发明申请公开(公告)号：US20090001481A1
公开(公告)日：2009-01-01
申请号：US11768270
申请日：2007-06-26
申请人： Ethan Harrison Cannon , Toshiharu Furukawa , David Vaclav Horak , Jack A. Mandelman , William Robert Tonti
发明人： Ethan Harrison Cannon , Toshiharu Furukawa , David Vaclav Horak , Jack A. Mandelman , William Robert Tonti
IPC分类号： H01L27/105 , H01L21/8238
CPC分类号： H01L27/0733 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L28/40
摘要： A semiconductor structure and a method for forming the same. The semiconductor structure includes (a) a semiconductor substrate, (b) a shallow trench isolation (STI) region on the semiconductor substrate, and (c) a first semiconductor transistor on the semiconductor substrate. The first semiconductor transistor includes (I) a first source/drain region, (ii) a second source/drain region, and (iii) a first gate electrode region. The first and second source/drain regions are doped with a same doping polarity. The semiconductor structure further includes a first doped region in the semiconductor substrate. The first doped region is on a first side wall and a bottom wall of the STI region. The first doped region is in direct physical contact with the second source/drain region. The first doped region and the second source/drain region are doped with a same doping polarity.
摘要翻译： 半导体结构及其形成方法。 半导体结构包括（a）半导体衬底，（b）半导体衬底上的浅沟槽隔离（STI）区域，以及（c）半导体衬底上的第一半导体晶体管。 第一半导体晶体管包括（I）第一源极/漏极区域，（ii）第二源极/漏极区域，以及（iii）第一栅极电极区域。 第一和第二源/漏区掺杂相同的掺杂极性。 半导体结构还包括在半导体衬底中的第一掺杂区域。 第一掺杂区域位于STI区域的第一侧壁和底壁上。 第一掺杂区域与第二源极/漏极区域直接物理接触。 第一掺杂区域和第二源极/漏极区域掺杂相同的掺杂极性。
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公开(公告)号：US07397692B1
公开(公告)日：2008-07-08
申请号：US11612809
申请日：2006-12-19
申请人： Ethan Harrison Cannon , Toshiharu Furukawa , David Vaclav Horak , Charles William Koburger, III , Jack A. Mandelman
发明人： Ethan Harrison Cannon , Toshiharu Furukawa , David Vaclav Horak , Charles William Koburger, III , Jack A. Mandelman
IPC分类号： G11C11/00
CPC分类号： G11C11/4125
摘要： An SRAM cell. The SRAM cell includes a first CMOS inverter and a second CMOS inverter, an input of the first inverter connected to an output of the second inverter and an input of the second inverter connected to an output of the first inverter, a first MOSFET interposed between an output of the first CMOS inverter and a first plate of a first capacitor, a second plate of the first capacitor connected to a high voltage terminal of a power supply; a second MOSFET interposed between an output of the second CMOS inverter and a first plate of a second capacitor, a second plate of the second capacitor connected to the high voltage terminal of the power supply; and a control signal line connected to a gate of the first MOSFET and a gate of the second MOSFET.
摘要翻译： 一个SRAM单元。 SRAM单元包括第一CMOS反相器和第二CMOS反相器，连接到第二反相器的输出的第一反相器的输入和连接到第一反相器的输出的第二反相器的输入， 第一CMOS反相器的输出和第一电容器的第一板，第一电容器的第二板连接到电源的高电压端子; 插入在所述第二CMOS反相器的输出端和第二电容器的第一板之间的第二MOSFET，所述第二电容器的第二板连接到所述电源的高电压端子; 以及连接到第一MOSFET的栅极和第二MOSFET的栅极的控制信号线。
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19.发明授权公开(公告)号：US07375339B2
公开(公告)日：2008-05-20
申请号：US11380736
申请日：2006-04-28
IPC分类号： G01T1/02
CPC分类号： G01T1/244
摘要： A method, device and system for monitoring ionizing radiation. The method including: collecting an ionizing radiation induced charge collected by the depletion region of a diode formed in a silicon layer below an oxide layer buried below a surface of a silicon substrate; and coupling a cathode of the diode to a precharged node of a clocked logic circuit such that the ionizing radiation induced charge collected by a depletion region of the diode will discharge the precharged node and change an output state of the clocked logic circuit.
摘要翻译： 一种用于监测电离辐射的方法，装置和系统。 该方法包括：收集由埋在硅衬底表面下方的氧化物层下面的硅层中形成的二极管的耗尽区收集的电离辐射感应电荷; 以及将二极管的阴极耦合到时钟逻辑电路的预充电节点，使得由二极管的耗尽区收集的电离辐射感应电荷将放电预充电节点并改变时钟逻辑电路的输出状态。
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