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公开(公告)号：US07286569B2
公开(公告)日：2007-10-23
申请号：US10314052
申请日：2002-12-06
申请人： Mounir Meghelli
发明人： Mounir Meghelli
IPC分类号： H04J3/06
CPC分类号： H04J3/0685
摘要： Apparatus for use in providing full-rate clock data retiming in a time division multiplexer, wherein the time division multiplexer includes an N to 1 time division multiplexer circuit and a retiming circuit, comprises the following circuitry. The apparatus comprises first circuitry for generating a half-rate clock from a full-rate clock used by the retiming circuit and for providing selective adjustment of a phase associated with the half-rate clock within a range of D degrees. The apparatus further comprises second circuitry, coupled to the first circuitry, for generating a set of sub-rate clocks from the phase-adjustable half-rate clock for use by the N to 1 time division multiplexer circuit in generating a multiplexed data stream from N parallel data streams, such that the retiming circuit is able to operate within a clock phase margin associated therewith. Phase adjustment need not be dependent on a rate associated with the multiplexed data stream, and may be continuous or discrete. When D is 180°, the retiming circuit is effectively able to operate with a clock phase margin of 360°.
摘要翻译： 用于在时分复用器中提供全速率时钟数据重新定时的装置，其中时分多路复用器包括N到1个时分多路复用器电路和重定时电路，包括以下电路。 该装置包括用于由重定时电路使用的全速率时钟产生半速率时钟的第一电路，并用于在D度范围内提供与半速率时钟相关联的相位的选择性调整。 该装置还包括耦合到第一电路的第二电路，用于从相位可调半速率时钟产生一组子速率时钟，供N到1个时分多路复用器电路使用以产生来自N的多路复用数据流 并行数据流，使得重定时电路能够在与其相关联的时钟相位裕度内工作。 相位调整不需要依赖于与多路复用数据流相关联的速率，并且可以是连续的或离散的。 当D为180°时，重新定时电路能够以360°的时钟相位裕度工作。
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公开(公告)号：US07741919B2
公开(公告)日：2010-06-22
申请号：US12114285
申请日：2008-05-02
IPC分类号： H03L7/00
CPC分类号： H03L7/0893 , H03L7/093 , H03L7/0998 , H03L2207/06
摘要： A voltage controlled oscillator and a method of operating a voltage-controlled oscillator are disclosed. The oscillator comprises a current controlled oscillator having a variable frequency current output, a first control path for generating a first control current having a first adjustable gain, and a second control path for generating a second control current having a second adjustable gain. A summer is provided for adding the first and second control currents to obtain a summed control current, and for applying the summed control current as an input current to the current controlled oscillator. A control sub-circuit is used for controlling the gain of the first control current as a function of a defined voltage on the second control path to maintain constant the gain of the current output of the current controlled oscillator over a given operating range of the current controlled oscillator.
摘要翻译： 公开了压控振荡器和操作压控振荡器的方法。 振荡器包括具有可变频率电流输出的电流控制振荡器，用于产生具有第一可调增益的第一控制电流的第一控制路径和用于产生具有第二可调增益的第二控制电流的第二控制路径。 提供一个加法器，用于增加第一和第二控制电流以获得相加的控制电流，并且将求和的控制电流作为输入电流施加到电流控制的振荡器。 控制子电路用于控制作为第二控制路径上的限定电压的函数的第一控制电流的增益，以在电流的给定工作范围内保持电流控制振荡器的电流输出的增益恒定 受控振荡器。
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13.发明申请公开(公告)号：US20080298530A1
公开(公告)日：2008-12-04
申请号：US12177231
申请日：2008-07-22
IPC分类号： H04L7/00
CPC分类号： H04L25/03343 , H03K5/135 , H03M9/00 , H04J3/047 , H04J3/0685 , H04L7/0037 , H04L25/03885
摘要： In the context of high-speed serial links, data-dependent jitter compensation techniques performed using phase pre-distortion. Broadly contemplated is an expansion of the notion of pre-emphasis beyond conventional amplitude compensation of ISI, whereby phase pre-emphasis for compensating data-dependent jitter (DDJ) is introduced. DDJ can be addressed by exploiting the relationship between the data sequence and the timing deviation. Phase pre-emphasis improves the signal integrity with little additional power consumption in the transmitter and with no cross-talk penalty.
摘要翻译： 在高速串行链路的上下文中，使用相位预失真执行的数据相关抖动补偿技术。 广泛考虑的是将预加重的概念扩展超出ISI的常规幅度补偿，由此引入用于补偿依赖于数据的抖动（DDJ）的相位预加重。 可以通过利用数据序列与时序偏差之间的关系来解决DDJ。 相位预加重提高了信号完整性，在发射机中几乎没有额外的功耗，没有串扰。
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14.发明申请公开(公告)号：US20080133958A1
公开(公告)日：2008-06-05
申请号：US11566576
申请日：2006-12-04
CPC分类号： G01R31/3171 , B82Y25/00 , G01R33/093
摘要： A method and system for determining the eye pattern margin parameters of a receiver system during diagnostic testing is presented. The circuitry in the receiver's front end comprises a series of latches, XOR gates and OR gates which first provide the data samples and edge samples, i.e., data sampled at the rising or falling edge of an (edge) clock characterized by a phase delay relative to the data sampling clock. The receiver also comprises optimization circuitry for the ideal alignment of the edge clock (edges) with the data edges. The method further provides for a phase shifting of the edge clock to the left and right from the ideal/locked position to screen the data eye pattern in order to compute the Bit Error Rate (BER) value. The position of the edge clock relative to the data sampling clock determines the horizontal eye opening for the computed BER.
摘要翻译： 提出了一种用于在诊断测试期间确定接收机系统的眼图边缘参数的方法和系统。 接收机前端的电路包括一系列锁存器，XOR门和OR门，它们首先提供数据样本和边缘样本，即在（边沿）时钟的上升沿或下降沿采样的数据，其特征在于相位延迟相对 到数据采样时钟。 接收机还包括用于边缘时钟（边缘）与数据边缘的理想对准的优化电路。 该方法还提供了边缘时钟从理想/锁定位置向左和向右移相以屏蔽数据眼图，以便计算误码率（BER）值。 边缘时钟相对于数据采样时钟的位置决定了计算的BER的水平眼睛开度。
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公开(公告)号：US06292065B1
公开(公告)日：2001-09-18
申请号：US09574089
申请日：2000-05-18
IPC分类号： H03B512
CPC分类号： H03B5/1231 , H03B5/1215 , H03B5/1253 , H03L7/099
摘要： The LC VCO includes an LC oscillator module with first and second tank nodes and a control module with positive and negative input voltage terminals. The control module includes four voltage dependent capacitive elements which are configured to be biased for operation as voltage dependent variable capacitances. The voltage dependent capacitive elements are interconnected such that the effect of a common mode input voltage is to increase the capacitance of two of the voltage dependent capacitive elements, while simultaneously decreasing the capacitance of two of the other voltage dependent capacitive elements by a substantially similar amount, such that a differential voltage applied across the positive and negative input voltage terminals is operable to change the capacitance of the voltage dependent capacitive elements, and thereby the frequency of the LC oscillator module, while effects on the output frequency of the oscillator caused by a common mode voltage tend to cancel. Accordingly, a fully differential signal path in phase locked loops employing LC oscillators, with improved noise rejection, substantial suppression of common mode noise, and a minimal increase in complexity over a single-ended control design can be achieved. Additional supply voltages need not be employed.
摘要翻译： LC VCO包括具有第一和第二储罐节点的LC振荡器模块和具有正和负输入电压端子的控制模块。 控制模块包括四个依赖于电压的电容元件，其被配置为被偏置用于作为电压相关的可变电容的操作。 电压相关的电容元件互连，使得共模输入电压的影响是增加两个电压相关的电容元件的电容，同时将两个其它依赖于电压的电容元件的电容降低大致相似的量 ，使得施加在正输入电压端子和负输入电压端子之间的差分电压可操作以改变电压相关电容元件的电容，从而改变LC振荡器模块的频率，同时对由振荡器的输出频率产生的影响由 共模电压倾向于取消。 因此，可以实现采用LC振荡器的锁相环中的完全差分信号路径，具有改进的噪声抑制，对共模噪声的实质性抑制，以及在单端控制设计上的最小复杂度增加。 不需要额外的电源电压。
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公开(公告)号：US07983368B2
公开(公告)日：2011-07-19
申请号：US11608948
申请日：2006-12-11
IPC分类号： H04L7/00
CPC分类号： H04L7/042 , H04L7/0004 , H04L7/0334
摘要： A sampling clock signal controller for receivers of digital data is disclosed. Specific bit patterns of a data waveform can be identified, and stored time samples of the waveform that correspond to the specific bit patterns can be analyzed to improve the timing of a sampling clock signal. These “time-amplitude” samples on known bit patterns can be utilized to determine if a sample on the data waveform should be taken before the center of the eye pattern, at the center of the eye pattern, or after the center of the eye pattern and by what time change. Accordingly, a single low power clock can be utilized to adjust the timing of the sample clock such that improved communication scan be achieved. Such a single clock system has reduced power requirements and increased accuracy.
摘要翻译： 公开了一种用于数字数据接收机的采样时钟信号控制器。 可以识别数据波形的特定位模式，并且可以分析对应于特定位模式的波形的存储时间采样以改善采样时钟信号的定时。 可以利用已知位图案上的这些“时间幅度”采样来确定数据波形上的样本是否应在眼图的中心，眼图的中心之前或眼图的中心之后 和什么时间改变。 因此，可以利用单个低功率时钟来调整采样时钟的定时，从而实现改进的通信扫描。 这种单一时钟系统降低了功率需求并提高了精度。
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公开(公告)号：US07945805B2
公开(公告)日：2011-05-17
申请号：US11930345
申请日：2007-10-31
申请人： Steven John Baumgartner , Anthony Richard Bonaccio , Timothy Clyde Buchholtz , Daniel Mark Dreps , Charles Porter Geer , Mounir Meghelli , Sergey Vladimirovich Rylov , David W. Siljenberg , Dana Marie Woeste
发明人： Steven John Baumgartner , Anthony Richard Bonaccio , Timothy Clyde Buchholtz , Daniel Mark Dreps , Charles Porter Geer , Mounir Meghelli , Sergey Vladimirovich Rylov , David W. Siljenberg , Dana Marie Woeste
IPC分类号： G06F1/10
CPC分类号： G06F13/4204 , Y02D10/14 , Y02D10/151
摘要： A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.
摘要翻译： 用于高速计算机处理器系统的设计结构包括用于图形处理器的高速接口。 在优选实施例中，高速接口包括与图形处理器上类似的高速接口相连接的前端总线（FSB）。
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公开(公告)号：US07624297B2
公开(公告)日：2009-11-24
申请号：US11610063
申请日：2006-12-13
申请人： Steven John Baumgartner , Anthony Richard Bonaccio , Timothy Clyde Buchholtz , Daniel Mark Dreps , Charles Porter Geer , Mounir Meghelli , Sergey Vladimirovich Rylov , David W. Siljenberg , Dana Marie Woeste
发明人： Steven John Baumgartner , Anthony Richard Bonaccio , Timothy Clyde Buchholtz , Daniel Mark Dreps , Charles Porter Geer , Mounir Meghelli , Sergey Vladimirovich Rylov , David W. Siljenberg , Dana Marie Woeste
IPC分类号： G06F1/10
CPC分类号： G06F13/4204 , Y02D10/14 , Y02D10/151
摘要： A high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.
摘要翻译： 高速计算机处理器系统包括用于图形处理器的高速接口。 在优选实施例中，高速接口包括与图形处理器上的类似高速接口相连接的前端总线（FSB）。
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19.发明申请公开(公告)号：US20090273405A1
公开(公告)日：2009-11-05
申请号：US12114285
申请日：2008-05-02
IPC分类号： H03L5/00
CPC分类号： H03L7/0893 , H03L7/093 , H03L7/0998 , H03L2207/06
摘要： A voltage controlled oscillator and a method of operating a voltage-controlled oscillator are disclosed. The oscillator comprises a current controlled oscillator having a variable frequency current output, a first control path for generating a first control current having a first adjustable gain, and a second control path for generating a second control current having a second adjustable gain. A summer is provided for adding the first and second control currents to obtain a summed control current, and for applying the summed control current as an input current to the current controlled oscillator. A control sub-circuit is used for controlling the gain of the first control current as a function of a defined voltage on the second control path to maintain constant the gain of the current output of the current controlled oscillator over a given operating range of the current controlled oscillator.
摘要翻译： 公开了压控振荡器和操作压控振荡器的方法。 振荡器包括具有可变频率电流输出的电流控制振荡器，用于产生具有第一可调增益的第一控制电流的第一控制路径和用于产生具有第二可调增益的第二控制电流的第二控制路径。 提供一个加法器，用于增加第一和第二控制电流以获得相加的控制电流，并且将求和的控制电流作为输入电流施加到电流控制的振荡器。 控制子电路用于控制作为第二控制路径上的限定电压的函数的第一控制电流的增益，以在电流的给定工作范围内保持电流控制振荡器的电流输出的增益恒定 受控振荡器。
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公开(公告)号：US07538652B2
公开(公告)日：2009-05-26
申请号：US11512014
申请日：2006-08-29
申请人： Keith A. Jenkins , Mounir Meghelli
发明人： Keith A. Jenkins , Mounir Meghelli
IPC分类号： H01F5/00
CPC分类号： H01F17/0013 , H01F21/12 , H01F41/045 , H01F2021/125 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , H05K1/165 , H01L2924/00
摘要： Techniques are disclosed for fabricating tunable electrical components in integrated circuits. For example, a method of tuning a value of an electrical component, such as a planar inductor, includes the steps of placing a conductive layer in proximity of the electrical component, and adjusting an amount of material that constitutes the conductive layer such that the value of the electrical component is tuned to a particular value. The adjustment step may be performed so as to select a frequency band with which the inductor is associated or to correct a manufacturing deviation in a frequency with which the inductor is associated.
摘要翻译： 公开了用于在集成电路中制造可调电气部件的技术。 例如，调整诸如平面电感器的电气部件的值的方法包括以下步骤：将导电层放置在电气部件附近，并且调整构成导电层的材料的量，使得值 的电气元件被调谐到特定的值。 可以执行调整步骤以便选择与电感器相关联的频带或者校正与电感器相关联的频率中的制造偏差。
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