公开(公告)号：US20060063177A1

公开(公告)日：2006-03-23

申请号：US11189064

申请日：2005-07-25

申请人： Roderick Bunch ,  Dale Morris ,  Sandra Curtiss ,  Charles Rodi

发明人： Roderick Bunch ,  Dale Morris ,  Sandra Curtiss ,  Charles Rodi

IPC分类号： C12Q1/68

摘要： The present invention relates to carcinogenesis biomarkers produced by phenobarbitol-treated rat hepatocytes, nucleic acid molecules that encode carcinogenesis biomarkers or a fragment thereof and nucleic acid molecules that are useful as probes or primers for detecting or inducing carcinogenesis, respectively. The invention also relates to applications of the factor or fragment such as forming antibodies capable of binding the carcinogenesis biomarkers or fragments thereof.

摘要翻译： 本发明涉及由苯巴比妥治疗的大鼠肝细胞产生的致癌生物​​标志物，编码致癌生物标志物的核酸分子或其片段，以及可用作探测或诱导癌发生的探针或引物的核酸分子。 本发明还涉及因子或片段的应用，例如形成能够结合致癌生物标志物或其片段的抗体。

公开(公告)号：US07424597B2

公开(公告)日：2008-09-09

申请号：US10403785

申请日：2003-03-31

申请人： Ruby B. Lee ,  Dale Morris

发明人： Ruby B. Lee ,  Dale Morris

IPC分类号： G06F9/312 ,  G06F9/315

CPC分类号： G06F9/30032 ,  G06F9/3004

摘要： Parallel table lookups are implemented using variable Mux instructions to reorder data. Table data can be represented in a “table” register, while the desired ordering can be represented in an “Index” register. A direct variable Mux instruction can specify the table register and the index register as arguments, along with a result register. The instruction writes at least some of the data from the table register into the result register as specified in the index register. If the entire table cannot fit within a single register, entries can be divided between two or more table registers. An indirect variable Mux instruction can specify both a table-register-select register and a subword-location-select register. Both the direct and indirect Mux instructions can be used with entry data that is divided in accordance with significance between registers. In that case, plural Mux instructions are used with UnPack instructions that concatenate portions of the table entries.

摘要翻译： 使用变量Mux指令实现并行表查找，以重新排序数据。 表数据可以在“表”寄存器中表示，而所需的顺序可以在“索引”寄存器中表示。 直接变量Mux指令可以指定表寄存器和索引寄存器作为参数，以及结果寄存器。 该指令将表寄存器中的至少一些数据写入索引寄存器中指定的结果寄存器。 如果整个表不能放在单个寄存器中，则可以在两个或多个表寄存器之间划分条目。 间接变量Mux指令可以指定表寄存器选择寄存器和子字选择寄存器。 直接和间接MUX指令都可以与根据寄存器之间的重要性划分的条目数据一起使用。 在这种情况下，多个Mux指令用于连接表项部分的UnPack指令。

公开(公告)号：US07281116B2

公开(公告)日：2007-10-09

申请号：US10903200

申请日：2004-07-30

申请人： Jonathan K. Ross ,  Dale Morris

发明人： Jonathan K. Ross ,  Dale Morris

IPC分类号： G06F12/00

CPC分类号： G06F12/1027 ,  G06F2212/682

摘要： The present invention provides a multiprocessor system and method in which plural memory locations are used for storing TLB-shootdown data respectively for plural processors. In contrast to systems in which a single area of memory serves for all processors' TLB-shootdown data, different processors can describe the memory they want to free concurrently. Thus, concurrent TLB-shootdown request are less likely to result in performance-limiting TLB-shootdown contentions that have previously constrained the scaleability of multiprocessor systems.

摘要翻译： 本发明提供一种多处理器系统和方法，其中使用多个存储器位置来分别存储用于多个处理器的TLB击倒数据。 与其中单个存储器区域用于所有处理器的TLB击倒数据的系统相反，不同的处理器可以描述他们想要同时释放的存储器。 因此，并发的TLB-downdown请求不太可能导致先前限制多处理器系统可扩展性的性能限制TLB击倒争用。

公开(公告)号：USD625525S1

公开(公告)日：2010-10-19

申请号：US29357578

申请日：2010-03-14

申请人： Dale Morris

设计人： Dale Morris

公开(公告)号：US07103756B2

公开(公告)日：2006-09-05

申请号：US10261131

申请日：2002-09-30

申请人： Dale Morris

发明人： Dale Morris

IPC分类号： G06F9/34

CPC分类号： G06F9/30036 ,  G06F9/30109 ,  G06F9/3838

摘要： A data processor includes program registers with individual byte-location write enables. Bypass networks allow a precision pipeline to respond to read requests by accessing a program register or pipeline stage on a byte-by-byte basis. The data processor can thus write to individual byte locations without overwriting other byte locations within the same register. The data processor has an instruction set with instructions that combine two operands and yield a one-byte result that is stored in a specified byte location of a specified result register. Eight instances of this instruction can pack eight results into a single 64-bit result register without additional packing instructions and without using a read port to read the result register before writing to it. As plural functional units can write concurrently to different subwords of the same result register, a system with four functional units can pack eight results into a result register in two instruction cycles.

摘要翻译： 数据处理器包括具有单个字节位置写入使能的程序寄存器。 旁路网络允许精确流水线通过以逐个字节的方式访问程序寄存器或流水线阶段来响应读请求。 因此，数据处理器可以写入单独的字节位置，而不会覆盖同一寄存器内的其他字节位置。 数据处理器具有指令集，其指令组合两个操作数，并产生存储在指定结果寄存器的指定字节位置的一字节结果。 该指令的八个实例可以将八个结果包装到单个64位结果寄存器中，无需附加的打包指令，并且在写入之前不使用读取端口读取结果寄存器。 由于多个功能单元可以同时写入相同结果寄存器的不同子字，所以具有四个功能单元的系统可以在两个指令周期内将八个结果封装到结果寄存器中。

公开(公告)号：US07085989B2

公开(公告)日：2006-08-01

申请号：US10414705

申请日：2003-04-15

申请人： Sverre Jarp ,  Dale Morris

发明人： Sverre Jarp ,  Dale Morris

IPC分类号： H03M13/00

CPC分类号： G06F9/30018 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036

摘要： A method for comparing bit field contents for bit fields comprising less than a full complement of the source is provided. The method includes creating a mask covering the bit field in the source, setting bit positions within the mask that are outside the bit field in the source to predetermined values, combining the source against the mask to form an intermediate result, and comparing bits in the intermediate result to provide a final result. Alternately, the method may form a mask, combining the bit field with a comparison value to form an intermediate value, and perform a combined function using the mask to select bits from the intermediate value, or fixed zero or one values, and comparing this result with zero.

摘要翻译： 提供了一种用于比较包括小于源的完整补码的比特字段的比特字段内容的方法。 该方法包括创建覆盖源中的位字段的掩码，将源内的位域之外的掩码内的位位置设置为预定值，将源与掩码组合以形成中间结果，并且比较 中间结果提供最终结果。 或者，该方法可以形成掩模，将比特字段与比较值组合以形成中间值，并且使用掩码执行组合函数以从中间值或固定的零或一个值中选择比特，并将该结果进行比较 零。

公开(公告)号：US07080242B2

公开(公告)日：2006-07-18

申请号：US10324345

申请日：2002-12-19

申请人： Dale Morris

发明人： Dale Morris

IPC分类号： G06F15/177 ,  G06F9/30

CPC分类号： G06F15/177 ,  G06F9/4405 ,  G06F9/5044

摘要： In a symmetric multiprocessing system using processors (DP0–DP7) of different capabilities (instruction sets), a processor responds (S11) to a query regarding its capabilities (instruction set) with its “active” capability, which is the intersection of its native capability and a common capability across processors determined (S04) during a boot sequence (13). The querying application (29) can select (S12) a program variant optimized for the active capability of the selected processor. If the application is subsequently subjected to a blind transfer to another processor, it is more likely than it would otherwise be (if the processors responded with their native capabilities) that the previously selected program variant runs without encountering unimplemented instructions.

摘要翻译： 在使用具有不同能力（指令集）的处理器（DP 0 -DP 7）的对称多处理系统中，处理器以其“有效”能力（即交点）对其能力（指令集）的查询作出响应（S11） 的启动顺序（13）中的自身能力和跨处理器（S 04）的共同功能。 查询应用程序（29）可以选择（S12）针对所选择的处理器的活动能力优化的程序变量。 如果应用程序随后受到盲目转移到另一个处理器，那么比以前选择的程序变体运行而不会遇到未实现的指令更有可能（如果处理器以其本机能力作出响应）。

公开(公告)号：US20060026408A1

公开(公告)日：2006-02-02

申请号：US10903155

申请日：2004-07-30

申请人： Dale Morris ,  James McCormick

发明人： Dale Morris ,  James McCormick

IPC分类号： G06F9/00

CPC分类号： G06F9/3846 ,  G06F9/3848

摘要： The present invention provides a system and method for runtime updating of hints in program instructions. The invention also provides for programs of instructions that include hint performance data. Also, the invention provides an instruction cache that modifies hints and writes them back. As runtime hint updates are stored in instructions, the impact of the updates is not limited by the limited memory capacity local to a processor. Also, there is no conflict between hardware and software hints, as they can share a common encoding in the program instructions.

公开(公告)号：US06611910B2

公开(公告)日：2003-08-26

申请号：US09169868

申请日：1998-10-12

申请人： Harshvardhan Sharangpani ,  Tse-Yu Yeh ,  Michael Paul Corwin ,  Millind Mittal ,  Kent G. Fielden ,  Dale Morris ,  Rajiv Gupta ,  Michael Schlansker ,  Mircea Poplingher

发明人： Harshvardhan Sharangpani ,  Tse-Yu Yeh ,  Michael Paul Corwin ,  Millind Mittal ,  Kent G. Fielden ,  Dale Morris ,  Rajiv Gupta ,  Michael Schlansker ,  Mircea Poplingher

IPC分类号： G06F930

CPC分类号： G06F9/3806 ,  G06F9/322 ,  G06F9/325 ,  G06F9/3844 ,  G06F9/3846

摘要： A branch operation is processed using a branch predict instruction and an associated branch instruction. The branch predict instruction indicates a predicted direction, a target address, and an instruction address for the associated branch instruction. When the branch predict instruction is detected, the target address is stored at an entry indicated by the associated branch instruction address and a prefetch request is triggered to the target address. The branch predict instruction may also include hint information for managing the storage and use of the branch prediction information.

摘要翻译： 使用分支预测指令和相关联的分支指令来处理分支操作。 分支预测指示指示相关联的分支指令的预测方向，目标地址和指令地址。 当检测到分支预测指令时，目标地址被存储在由关联的分支指令地址指示的条目上，并且预取请求被触发到目标地址。 分支预测指令还可以包括用于管理分支预测信息的存储和使用的提示信息。

公开(公告)号：US06438682B1

公开(公告)日：2002-08-20

申请号：US09169866

申请日：1998-10-12

申请人： Dale Morris ,  Mircea Poplingher ,  Tse-Yu Yeh ,  Michael P. Corwin ,  Wenliang Chen

发明人： Dale Morris ,  Mircea Poplingher ,  Tse-Yu Yeh ,  Michael P. Corwin ,  Wenliang Chen

IPC分类号： G06F932

CPC分类号： G06F9/325

摘要： A loop branch prediction system is provided to predict a final iteration of a loop and resteer an associated fetch module to an appropriate target address. The loop prediction system includes a counter and an end of loop (EOL) module. In one mode, the counter tracks loop branches in process. When a termination condition is detected, the counter switches to a second mode to track the number of loop branches still to be issued. The EOL module compares the number of loop branches still to be issued with one or more threshold values and generates a resteer signal when a match is detected.

摘要翻译： 提供循环分支预测系统以预测循环的最终迭代并将相关联的获取模块修复到适当的目标地址。 环路预测系统包括计数器和结束循环（EOL）模块。 在一种模式下，计数器跟踪正在进行的循环分支。 当检测到终止条件时，计数器切换到第二模式以跟踪仍然发布的循环分支的数量。 EOL模块将仍然要发出的环路分支数与一个或多个阈值进行比较，并在检测到匹配时产生一个恢复信号。