利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

37 条记录 (耗时 0.037 秒)

    Method and apparatus for predicting loop exit branches
    1.
    发明授权
    Method and apparatus for predicting loop exit branches 有权
    用于预测环路出口分支的方法和装置

    公开(公告)号：US06438682B1

    公开(公告)日：2002-08-20

    申请号：US09169866

    申请日：1998-10-12

    申请人： Dale Morris ,  Mircea Poplingher ,  Tse-Yu Yeh ,  Michael P. Corwin ,  Wenliang Chen

    发明人： Dale Morris ,  Mircea Poplingher ,  Tse-Yu Yeh ,  Michael P. Corwin ,  Wenliang Chen

    IPC分类号： G06F932

    CPC分类号： G06F9/325

    摘要： A loop branch prediction system is provided to predict a final iteration of a loop and resteer an associated fetch module to an appropriate target address. The loop prediction system includes a counter and an end of loop (EOL) module. In one mode, the counter tracks loop branches in process. When a termination condition is detected, the counter switches to a second mode to track the number of loop branches still to be issued. The EOL module compares the number of loop branches still to be issued with one or more threshold values and generates a resteer signal when a match is detected.

    摘要翻译： 提供循环分支预测系统以预测循环的最终迭代并将相关联的获取模块修复到适当的目标地址。 环路预测系统包括计数器和结束循环（EOL）模块。 在一种模式下，计数器跟踪正在进行的循环分支。 当检测到终止条件时，计数器切换到第二模式以跟踪仍然发布的循环分支的数量。 EOL模块将仍然要发出的环路分支数与一个或多个阈值进行比较，并在检测到匹配时产生一个恢复信号。

    Instruction prefetch mechanism utilizing a branch predict instruction
    2.
    发明授权
    Instruction prefetch mechanism utilizing a branch predict instruction 失效
    使用分支预测指令的指令预取机制

    公开(公告)号：US5742804A

    公开(公告)日：1998-04-21

    申请号：US685607

    申请日：1996-07-24

    申请人： Tse-Yu Yeh ,  Mircea Poplingher ,  Kent G. Fielden ,  Hans Mulder ,  Rajiv Gupta ,  Dale Morris ,  Michael Schlansker

    发明人： Tse-Yu Yeh ,  Mircea Poplingher ,  Kent G. Fielden ,  Hans Mulder ,  Rajiv Gupta ,  Dale Morris ,  Michael Schlansker

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3804 ,  G06F9/3836 ,  G06F9/3846

    摘要： A processor and method that reduces instruction fetch penalty in the execution of a program sequence of instructions comprises a branch predict instruction that is inserted into the program at a location which precedes the branch. The branch predict instruction has an opcode that specifies a branch as likely to be taken or not taken, and which also specifies a target address of the branch. A block of target instructions, starting at the target address, is prefetched into the instruction cache of the processor so that the instructions are available for execution prior to the point in the program where the branch is encountered. Also specified by the opcode is an indication of the size of the block of target instructions, and a trace vector of a path in the program sequence that leads to the target from the branch predict instruction for better utilization of limited memory bandwidth.

    摘要翻译： 在程序指令序列的执行中减少指令提取损失的处理器和方法包括在分支之前的位置处插入到程序中的分支预测指令。 分支预测指令具有指定可能被采用或未被采用的分支的操作​​码，并且还指定分支的目标地址。 从目标地址开始的目标指令块被预取到处理器的指令高速缓存中，使得指令在程序中遇到分支的点之前可用于执行。 操作码还指定了目标指令块的大小的指示，以及由分支预测指令导致目标的程序序列中的路径的跟踪向量，以更好地利用有限的存储器带宽。

    Biomarkers and assays for carcinogenesis
    7.
    发明申请
    Biomarkers and assays for carcinogenesis 审中-公开
    生物标志物和致癌作用的测定

    公开(公告)号：US20060063177A1

    公开(公告)日：2006-03-23

    申请号：US11189064

    申请日：2005-07-25

    申请人： Roderick Bunch ,  Dale Morris ,  Sandra Curtiss ,  Charles Rodi

    发明人： Roderick Bunch ,  Dale Morris ,  Sandra Curtiss ,  Charles Rodi

    IPC分类号： C12Q1/68

    摘要： The present invention relates to carcinogenesis biomarkers produced by phenobarbitol-treated rat hepatocytes, nucleic acid molecules that encode carcinogenesis biomarkers or a fragment thereof and nucleic acid molecules that are useful as probes or primers for detecting or inducing carcinogenesis, respectively. The invention also relates to applications of the factor or fragment such as forming antibodies capable of binding the carcinogenesis biomarkers or fragments thereof.

    摘要翻译： 本发明涉及由苯巴比妥治疗的大鼠肝细胞产生的致癌生物​​标志物，编码致癌生物标志物的核酸分子或其片段，以及可用作探测或诱导癌发生的探针或引物的核酸分子。 本发明还涉及因子或片段的应用，例如形成能够结合致癌生物标志物或其片段的抗体。

    Variable reordering (Mux) instructions for parallel table lookups from registers
    9.
    发明授权
    Variable reordering (Mux) instructions for parallel table lookups from registers 失效
    来自寄存器的并行表查找的可变重排序（Mux）指令

    公开(公告)号：US07424597B2

    公开(公告)日：2008-09-09

    申请号：US10403785

    申请日：2003-03-31

    申请人： Ruby B. Lee ,  Dale Morris

    发明人： Ruby B. Lee ,  Dale Morris

    IPC分类号： G06F9/312 ,  G06F9/315

    CPC分类号： G06F9/30032 ,  G06F9/3004

    摘要： Parallel table lookups are implemented using variable Mux instructions to reorder data. Table data can be represented in a “table” register, while the desired ordering can be represented in an “Index” register. A direct variable Mux instruction can specify the table register and the index register as arguments, along with a result register. The instruction writes at least some of the data from the table register into the result register as specified in the index register. If the entire table cannot fit within a single register, entries can be divided between two or more table registers. An indirect variable Mux instruction can specify both a table-register-select register and a subword-location-select register. Both the direct and indirect Mux instructions can be used with entry data that is divided in accordance with significance between registers. In that case, plural Mux instructions are used with UnPack instructions that concatenate portions of the table entries.

    摘要翻译： 使用变量Mux指令实现并行表查找，以重新排序数据。 表数据可以在“表”寄存器中表示，而所需的顺序可以在“索引”寄存器中表示。 直接变量Mux指令可以指定表寄存器和索引寄存器作为参数，以及结果寄存器。 该指令将表寄存器中的至少一些数据写入索引寄存器中指定的结果寄存器。 如果整个表不能放在单个寄存器中，则可以在两个或多个表寄存器之间划分条目。 间接变量Mux指令可以指定表寄存器选择寄存器和子字选择寄存器。 直接和间接MUX指令都可以与根据寄存器之间的重要性划分的条目数据一起使用。 在这种情况下，多个Mux指令用于连接表项部分的UnPack指令。

    Multiprocessor system having plural memory locations for respectively storing TLB-shootdown data for plural processor nodes
    10.
    发明授权
    Multiprocessor system having plural memory locations for respectively storing TLB-shootdown data for plural processor nodes 失效
    具有用于分别存储用于多个处理器节点的TLB击落数据的多个存储器位置的多处理器系统

    公开(公告)号：US07281116B2

    公开(公告)日：2007-10-09

    申请号：US10903200

    申请日：2004-07-30

    申请人： Jonathan K. Ross ,  Dale Morris

    发明人： Jonathan K. Ross ,  Dale Morris

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1027 ,  G06F2212/682

    摘要： The present invention provides a multiprocessor system and method in which plural memory locations are used for storing TLB-shootdown data respectively for plural processors. In contrast to systems in which a single area of memory serves for all processors' TLB-shootdown data, different processors can describe the memory they want to free concurrently. Thus, concurrent TLB-shootdown request are less likely to result in performance-limiting TLB-shootdown contentions that have previously constrained the scaleability of multiprocessor systems.

    摘要翻译： 本发明提供一种多处理器系统和方法，其中使用多个存储器位置来分别存储用于多个处理器的TLB击倒数据。 与其中单个存储器区域用于所有处理器的TLB击倒数据的系统相反，不同的处理器可以描述他们想要同时释放的存储器。 因此，并发的TLB-downdown请求不太可能导致先前限制多处理器系统可扩展性的性能限制TLB击倒争用。