公开(公告)号：US5852576A

公开(公告)日：1998-12-22

申请号：US944904

申请日：1997-10-06

申请人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Charles Hollmer ,  Shoichi Kawamura ,  Michael Shingche Chung ,  Vincent C. Leung ,  Masaru Yano

发明人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Charles Hollmer ,  Shoichi Kawamura ,  Michael Shingche Chung ,  Vincent C. Leung ,  Masaru Yano

IPC分类号： G11C16/06 ,  G11C8/08 ,  G11C16/12 ,  G11C13/00

CPC分类号： G11C16/12 ,  G11C8/08

摘要： Two NMOS boost transistors have their sources connected to the high voltage input while their drains and gates are cross-connected. Two coupling capacitors connect two alternate phase clocks to the gates of the two cross-connected boost transistors. An NMOS pass transistor has its gate connected to the drain of one of the NMOS boost transistors, its source connected to the high voltage input, and its drain connected to the output. In an embodiment, two diode-connected regulation transistors connect the gates of the boost transistors to the high voltage input. These connections insure that the gates of the boost transistors and the gate of the pass transistor never reach voltages higher than one threshold voltage above the high voltage input. In another embodiment, two discharge transistors have their drains connected to a decode input, their sources connected to the gates of the boost transistors, and their gates connected to the positive power supply. By setting the decode input at zero volts, the voltages at the gates of the boost transistors and of the pass transistor are held at zero volts, thus disabling them. In the preferred embodiment, both the regulation transistors and the discharge transistors are included in the high voltage pass gate.

摘要翻译： 两个NMOS升压晶体管的源极连接到高压输入端，而它们的漏极和栅极交叉连接。 两个耦合电容器将两个交替相位时钟连接到两个交叉连接的升压晶体管的栅极。 NMOS传输晶体管的栅极连接到一个NMOS升压晶体管的漏极，其源极连接到高压输入，其漏极连接到输出。 在一个实施例中，两个二极管连接的调节晶体管将升压晶体管的栅极连接到高电压输入。 这些连接确保升压晶体管的栅极和传输晶体管的栅极不会达到高于高电压输入以上的一个阈值电压的电压。 在另一个实施例中，两个放电晶体管的漏极连接到解码输入，其源极连接到升压晶体管的栅极，并且其栅极连接到正电源。 通过将解码输入设置为零伏特，升压晶体管和传输晶体管的栅极处的电压保持在零伏特，从而禁止它们。 在优选实施例中，调节晶体管和放电晶体管都包括在高压通栅中。

公开(公告)号：US5801579A

公开(公告)日：1998-09-01

申请号：US808237

申请日：1997-02-28

申请人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Hollmer ,  Shoichi Kawamura ,  Michael Chung ,  Vincent Leung ,  Masaru Yano

发明人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Hollmer ,  Shoichi Kawamura ,  Michael Chung ,  Vincent Leung ,  Masaru Yano

IPC分类号： G11C8/08 ,  G11C16/12 ,  G05F1/10

CPC分类号： G11C16/12 ,  G11C8/08

摘要： Two NMOS boost transistors have their sources connected to the high voltage input while their drains and gates are cross-connected. Two coupling capacitors connect two alternate phase clocks to the gates of the two cross-connected boost transistors. An NMOS pass transistor has its gate connected to the drain of one of the NMOS boost transistors, its source connected to the high voltage input, and its drain connected to the output. In an embodiment, two diode-connected regulation transistors connect the gates of the boost transistors to the high voltage input. These connections insure that the gates of the boost transistors and the gate of the pass transistor never reach voltages higher than one threshold voltage above the high voltage input. In another embodiment, two discharge transistors have their drains connected to a decode input, their sources connected to the gates of the boost transistors, and their gates connected to the positive power supply. By setting the decode input at zero volts, the voltages at the gates of the boost transistors and of the pass transistor are held at zero volts, thus disabling them. In the preferred embodiment, both the regulation transistors and the discharge transistors are included in the high voltage pass gate.

摘要翻译： 两个NMOS升压晶体管的源极连接到高压输入端，而它们的漏极和栅极交叉连接。 两个耦合电容器将两个交替相位时钟连接到两个交叉连接的升压晶体管的栅极。 NMOS传输晶体管的栅极连接到一个NMOS升压晶体管的漏极，其源极连接到高压输入，其漏极连接到输出。 在一个实施例中，两个二极管连接的调节晶体管将升压晶体管的栅极连接到高电压输入。 这些连接确保升压晶体管的栅极和传输晶体管的栅极不会达到高于高电压输入以上的一个阈值电压的电压。 在另一个实施例中，两个放电晶体管的漏极连接到解码输入，其源极连接到升压晶体管的栅极，并且其栅极连接到正电源。 通过将解码输入设置为零伏特，升压晶体管和传输晶体管的栅极处的电压保持在零伏特，从而禁止它们。 在优选实施例中，调节晶体管和放电晶体管都包括在高压通栅中。

公开(公告)号：US07076703B1

公开(公告)日：2006-07-11

申请号：US10305700

申请日：2002-11-26

申请人： Binh Quang Le ,  Pau-Ling Chen

发明人： Binh Quang Le ,  Pau-Ling Chen

IPC分类号： G11C29/00

CPC分类号： G11C29/804

摘要： A method for a memory redundancy, including a memory array typically having a plurality of columns (e.g., bit lines) of memory cells, and identifying a particular (e.g., defective) column of the memory array and further defining a redundancy window by selecting a group of adjacent columns including the defective column. The number of columns in the group of selected columns may be equal to the number of columns in a redundancy array that is coupled to the memory array. The redundancy array is used for storing information that would have been otherwise stored in the memory cells in the redundancy window. The selected group includes at least one column on one side of the defective column and another column on the other side of the defective column. Typically, there will be multiple columns on each side of the defective column.

摘要翻译： 一种用于存储器冗余的方法，包括通常具有存储器单元的多个列（例如，位线）的存储器阵列，以及识别存储器阵列的特定（例如，有缺陷的）列，并进一步通过选择一个 一组相邻列，包括有缺陷的列。 所选列组中的列数可以等于耦合到存储器阵列的冗余阵列中的列数。 冗余阵列用于存储否则将存储在冗余窗口中的存储器单元中的信息。 所选择的组包括在缺陷列的一侧上的至少一个列和在缺陷列的另一侧上的另一个列。 通常，有缺陷的列的每一侧将有多个列。

公开(公告)号：US06288951B1

公开(公告)日：2001-09-11

申请号：US09675940

申请日：2000-09-29

申请人： Pau-Ling Chen ,  Binh Quang Le

发明人： Pau-Ling Chen ,  Binh Quang Le

IPC分类号： G11C700

CPC分类号： G11C5/145

摘要： A non-volatile memory and method for continuously regulating an output of a charge pump of the non-volatile memory for long periods of time at a target output voltage.

摘要翻译： 一种非易失性存储器和方法，用于在目标输出电压下长时间持续地调节非易失性存储器的电荷泵的输出。

公开(公告)号：US06262469B1

公开(公告)日：2001-07-17

申请号：US09047237

申请日：1998-03-25

申请人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Charles Hollmer

发明人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Charles Hollmer

IPC分类号： H01L2900

CPC分类号： H01L29/94 ,  H01L27/0811 ,  H01L29/66189

摘要： A capacitor divider includes two capacitors coupled in series between two voltage sources. A first capacitor is a floating gate capacitor having one plate being the control gate of a floating gate transistor structure and the other plate being a source, drain, and channel region of the floating gate transistor structure. The capacitive divider has the advantage of having at least one floating gate capacitor, can be implemented in a voltage regulator, and works for a variety of voltages across the capacitors.

摘要翻译： 电容器分压器包括两个电容器，它们串联在两个电压源之间。 第一电容器是浮置栅极电容器，其中一个板是浮栅晶体管结构的控制栅极，另一个栅极是浮栅晶体管结构的源极，漏极和沟道区。 电容分压器的优点是具有至少一个浮置栅极电容器，可以在电压调节器中实现，并且可以用于跨越电容器的各种电压。

公开(公告)号：US6005804A

公开(公告)日：1999-12-21

申请号：US993634

申请日：1997-12-18

申请人： Shane C. Hollmer ,  Binh Quang Le ,  Pau-ling Chen

发明人： Shane C. Hollmer ,  Binh Quang Le ,  Pau-ling Chen

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/00

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： An EEPROM NAND array has floating gate memory cells coupled in series, each having a control gate, a floating gate, a body region, and an insulating layer between the floating gate and the body region. A negative charge pump is coupled to the body region. In programming, the body region of the memory cell selected for programming is biased to a negative voltage by the negative charge pump while the control gate of the memory cell is biased to a predetermined positive voltage sufficient to induce Fowler-Nordheim tunneling from the body region into the floating gate. The present invention allows the programming voltage requirement at the control gate of a NAND EEPROM memory cell to be significantly reduced which allows for the peripheral voltage delivery circuitry in NAND EEPROM arrays to be designed for lower voltages than for conventional NAND EEPROM arrays.

摘要翻译： EEPROM NAND阵列具有串联耦合的浮动栅极存储单元，每个浮动栅极存储单元在浮置栅极和体区之间具有控制栅极，浮动栅极，体区域和绝缘层。 负电荷泵耦合到身体区域。 在编程中，选择用于编程的存储单元的主体区域被负电荷泵偏置到负电压，而存储单元的控制栅极被偏置到预定的正电压以足以引导来自身体区域的Fowler-Nordheim隧穿 进入浮动门。 本发明允许NAND EEPROM存储单元的控制栅极上的编程电压要求显着降低，这允许NAND EEPROM阵列中的外围电压传送电路被设计为比传统的NAND EEPROM阵列更低的电压。

公开(公告)号：US5999452A

公开(公告)日：1999-12-07

申请号：US63688

申请日：1998-04-21

申请人： Pau-Ling Chen ,  Mike Van Buskirk ,  Shane Charles Hollmer ,  Binh Quang Le ,  Shoichi Kawamura ,  Chung-You Hu ,  Yu Sun ,  Sameer Haddad ,  Chi Chang

发明人： Pau-Ling Chen ,  Mike Van Buskirk ,  Shane Charles Hollmer ,  Binh Quang Le ,  Shoichi Kawamura ,  Chung-You Hu ,  Yu Sun ,  Sameer Haddad ,  Chi Chang

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C13/00

CPC分类号： G11C16/0483

摘要： A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.

摘要翻译： 串联选择晶体管和源选择晶体管串联连接在浮动数据存储晶体管的NAND串的末端。 浮置栅极，串联选择栅极和源选择栅极都优选由多晶硅形成。 相同的隧道氧化物层用作串联选择晶体管和源极选择晶体管以及浮动栅极数据存储晶体管的栅极氧化物。 串联选择栅极和源极选择栅极中的两层多晶硅结合在一起。 串联选择晶体管连接到NAND串中的最后一个晶体管。 源选择晶体管连接到阵列Vss电源。 为了在另一NAND单元的编程期间编程禁止特定NAND单元，串联选择晶体管的栅极升高到Vcc，同时源极选择晶体管的栅极保持接地。 串联的两个晶体管能够在NAND串的末端承受高得多的电压，而不会在串联或源极选择晶体管中产生门极二极管结或氧化物击穿。

公开(公告)号：US5995417A

公开(公告)日：1999-11-30

申请号：US175646

申请日：1998-10-20

申请人： Pau-Ling Chen ,  Michael S. C. Chung ,  Shane C. Hollmer ,  Vincent Leung ,  Binh Quang Le ,  Masaru Yano

发明人： Pau-Ling Chen ,  Michael S. C. Chung ,  Shane C. Hollmer ,  Vincent Leung ,  Binh Quang Le ,  Masaru Yano

IPC分类号： G11C16/02 ,  G11C16/16 ,  G11C16/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3445 ,  G11C16/16 ,  G11C16/344

摘要： A non-volatile memory device includes a plurality of MOS transistors 34 and 36 connected to respective word lines 16 and 18 to allow individual pages of memory stored in the memory cells 8a, 10a and 8b, 10b on the respective word lines 16 and 18 to be erased and erase verified. A method of erasing a page of memory cells includes the steps of applying an erase voltage to one of the MOS transistors 16 and 18 to erase the page of memory cells along the respective word line, and applying an initial erase-inhibit floating voltage to other MOS transistors which are connected to the word lines unselected for page erase. In an erase verify mode, an erase verify voltage is applied to the word line which was selected for page erase in the erase mode, and an erase verify unselect voltage is applied to the word lines which was not selected for page erase.

摘要翻译： 非易失性存储器件包括连接到各个字线16和18的多个MOS晶体管34和36，以允许存储在相应字线16和18上的存储器单元8a，10a和8b，10b中的存储器的各页 被擦除和擦除验证。 擦除一页存储单元的方法包括以下步骤：将擦除电压施加到MOS晶体管16和18中的一个以擦除沿着相应字线的存储单元的页面，并将初始擦除禁止浮动电压施加到其他 连接到未选择用于页面擦除的字线的MOS晶体管。 在擦除验证模式下，擦除验证电压被施加到在擦除模式下被选择用于页擦除的字线，并且擦除验证未选择电压被施加到未被选择用于页擦除的字线。

公开(公告)号：US5912489A

公开(公告)日：1999-06-15

申请号：US940674

申请日：1997-09-30

申请人： Pau-Ling Chen ,  Mike Van Buskirk ,  Shane Charles Hollmer ,  Binh Quang Le ,  Shoichi Kawamura ,  Chung-You Hu ,  Yu Sun ,  Sameer Haddad ,  Chi Chang

发明人： Pau-Ling Chen ,  Mike Van Buskirk ,  Shane Charles Hollmer ,  Binh Quang Le ,  Shoichi Kawamura ,  Chung-You Hu ,  Yu Sun ,  Sameer Haddad ,  Chi Chang

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0483

摘要： A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.

摘要翻译： 串联选择晶体管和源选择晶体管串联连接在浮动数据存储晶体管的NAND串的末端。 浮置栅极，串联选择栅极和源选择栅极都优选由多晶硅形成。 相同的隧道氧化物层用作串联选择晶体管和源极选择晶体管以及浮动栅极数据存储晶体管的栅极氧化物。 串联选择栅极和源极选择栅极中的两层多晶硅结合在一起。 串联选择晶体管连接到NAND串中的最后一个晶体管。 源选择晶体管连接到阵列Vss电源。 为了在另一NAND单元的编程期间编程禁止特定NAND单元，串联选择晶体管的栅极升高到Vcc，同时源极选择晶体管的栅极保持接地。 串联的两个晶体管能够在NAND串的末端承受高得多的电压，而不会在串联或源极选择晶体管中产生门极二极管结或氧化物击穿。

公开(公告)号：US06781417B1

公开(公告)日：2004-08-24

申请号：US10282459

申请日：2002-10-29

申请人： Binh Quang Le ,  Lee Cleveland ,  Pau-Ling Chen

发明人： Binh Quang Le ,  Lee Cleveland ,  Pau-Ling Chen

IPC分类号： H03K19185

CPC分类号： G05F3/242 ,  H03K19/018507

摘要： According to one exemplary embodiment, a buffer circuit is configured to receive a supply voltage and an input reference voltage, the buffer circuit has a first FET operating in saturation region where the source of the first FET is coupled to the output reference voltage. The first FET can be configured, for example, as an open-loop voltage follower and, by way of example, a first resistor can be used to couple the source of the first FET to the output reference voltage. A tracking circuit is connected to the buffer circuit. The tracking circuit comprises a second FET also operating in saturation region where the drain of the second FET is coupled to the output reference voltage. Both the first and second FETs can be, for example, depletion mode transistors.

摘要翻译： 根据一个示例性实施例，缓冲电路被配置为接收电源电压和输入参考电压，所述缓冲电路具有在饱和区域中工作的第一FET，其中第一FET的源极耦合到输出参考电压。 第一FET可以被配置为例如开环电压跟随器，并且作为示例，可以使用第一电阻器将第一FET的源极耦合到输出参考电压。 跟踪电路连接到缓冲电路。 跟踪电路包括也在饱和区域工作的第二FET，其中第二FET的漏极耦合到输出参考电压。 第一和第二FET都可以是例如耗尽型晶体管。