-
1.发明授权High voltage NMOS pass gate having supply range, area, and speed advantages 失效具有供电范围，面积和速度优势的高压NMOS通道门
公开(公告)号：US5844840A
公开(公告)日：1998-12-01
申请号：US914543
申请日：1997-08-19
CPC分类号： G11C8/08
摘要： According to an aspect of the embodiments, the block decoder control circuits which drive the pass transistors for the word lines for a flash memory array are driven with a control voltage that is regulated to be one enhancement transistors threshold voltage higher than the highest voltage that is actually driven onto the word lines. According to another aspect of some of the embodiments, the block decoder control circuits are implemented with transistors having a very low threshold voltage. According to yet another aspect of some of the embodiments, a special series connection is used to prevent any leakage current through the block decoder control circuit from the high voltage generating charge pumps which might otherwise result from the use of low threshold voltage transistors. In the special series connection, any leakage current occurs from the supply voltage source rather than from the high voltage generating charge pumps. According to still another aspect of some of the embodiments, a special gate connection applies an intermediate bias voltage higher than a positive supply voltage onto the gates of the unselected block decoder transistors that are connected to a high-voltage. Several embodiments are presented which combine the regulated control voltage aspect and various combinations of the other aspects.
摘要翻译： 根据实施例的一个方面，驱动用于闪存阵列的字线的传输晶体管的块解码器控制电路被控制电压驱动，该控制电压被调节为高于最高电压的一个增强晶体管阈值电压 实际上驱动到字线上。 根据一些实施例的另一方面，块解码器控制电路用具有非常低的阈值电压的晶体管来实现。 根据一些实施例的另一方面，使用特殊的串联连接来防止任何来自块解码器控制电路的泄漏电流与由高阈值电压晶体管使用而产生的高电压产生电荷泵。 在特殊的串联连接中，从电源电压源而不是高压发生电荷泵发生泄漏电流。 根据一些实施例的另一方面，特殊栅极连接将高于正电源电压的中间偏置电压施加到连接到高电压的未选择的块解码器晶体管的栅极上。 提出了组合调节的控制电压方面和其他方面的各种组合的几个实施例。
-
2.发明授权High voltage NMOS pass gate having supply range, area, and speed advantages 有权具有供电范围，面积和速度优势的高压NMOS通道门
公开(公告)号：US5909396A
公开(公告)日：1999-06-01
申请号：US127991
申请日：1998-08-03
CPC分类号： G11C8/08
摘要： According to an aspect of the embodiments, the block decoder control circuits which drive the pass transistors for the word lines for a flash memory array are driven with a control voltage that is regulated to be one enhancement transistor's threshold voltage higher than the highest voltage that is actually driven onto the word lines. According to another aspect of some of the embodiments, the block decoder control circuits are implemented with transistors having a very low threshold voltage. According to yet another aspect of some of the embodiments, a special series connection is used to prevent any leakage current through the block decoder control circuit from the high voltage generating charge pumps which might otherwise result from the use of low threshold voltage transistors. In the special series connection, any leakage current occurs from the supply voltage source rather than from the high voltage generating charge pumps. According to still another aspect of some of the embodiments, a special gate connection applies an intermediate bias voltage higher than a positive supply voltage onto the gates of the unselected block decoder transistors that are connected to a high-voltage. Several embodiments are presented which combine the regulated control voltage aspect and various combinations of the other aspects.
摘要翻译： 根据实施例的一个方面，驱动用于闪存阵列的字线的传输晶体管的块解码器控制电路被控制电压驱动，该控制电压被调节为高于最高电压的一个增强晶体管的阈值电压 实际上驱动到字线上。 根据一些实施例的另一方面，块解码器控制电路用具有非常低的阈值电压的晶体管来实现。 根据一些实施例的另一方面，使用特殊的串联连接来防止任何来自块解码器控制电路的泄漏电流与由高阈值电压晶体管使用而产生的高电压产生电荷泵。 在特殊的串联连接中，从电源电压源而不是高压发生电荷泵发生泄漏电流。 根据一些实施例的另一方面，特殊栅极连接将高于正电源电压的中间偏置电压施加到连接到高电压的未选择的块解码器晶体管的栅极上。 提出了组合调节的控制电压方面和其他方面的各种组合的几个实施例。
-
3.发明授权High voltage NMOS pass gate for integrated circuit with high voltage generator and flash non-volatile memory device having the pass gate 失效具有高电压发生器的集成电路的高电压NMOS通过栅极和具有通过栅极的闪存非易失性存储器件
公开(公告)号：US5852576A
公开(公告)日：1998-12-22
申请号：US944904
申请日：1997-10-06
申请人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer , Shoichi Kawamura , Michael Shingche Chung , Vincent C. Leung , Masaru Yano
发明人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer , Shoichi Kawamura , Michael Shingche Chung , Vincent C. Leung , Masaru Yano
摘要： Two NMOS boost transistors have their sources connected to the high voltage input while their drains and gates are cross-connected. Two coupling capacitors connect two alternate phase clocks to the gates of the two cross-connected boost transistors. An NMOS pass transistor has its gate connected to the drain of one of the NMOS boost transistors, its source connected to the high voltage input, and its drain connected to the output. In an embodiment, two diode-connected regulation transistors connect the gates of the boost transistors to the high voltage input. These connections insure that the gates of the boost transistors and the gate of the pass transistor never reach voltages higher than one threshold voltage above the high voltage input. In another embodiment, two discharge transistors have their drains connected to a decode input, their sources connected to the gates of the boost transistors, and their gates connected to the positive power supply. By setting the decode input at zero volts, the voltages at the gates of the boost transistors and of the pass transistor are held at zero volts, thus disabling them. In the preferred embodiment, both the regulation transistors and the discharge transistors are included in the high voltage pass gate.
摘要翻译： 两个NMOS升压晶体管的源极连接到高压输入端，而它们的漏极和栅极交叉连接。 两个耦合电容器将两个交替相位时钟连接到两个交叉连接的升压晶体管的栅极。 NMOS传输晶体管的栅极连接到一个NMOS升压晶体管的漏极，其源极连接到高压输入，其漏极连接到输出。 在一个实施例中，两个二极管连接的调节晶体管将升压晶体管的栅极连接到高电压输入。 这些连接确保升压晶体管的栅极和传输晶体管的栅极不会达到高于高电压输入以上的一个阈值电压的电压。 在另一个实施例中，两个放电晶体管的漏极连接到解码输入，其源极连接到升压晶体管的栅极，并且其栅极连接到正电源。 通过将解码输入设置为零伏特，升压晶体管和传输晶体管的栅极处的电压保持在零伏特，从而禁止它们。 在优选实施例中，调节晶体管和放电晶体管都包括在高压通栅中。
-
4.发明授权Capacitor for use in a capacitor divider that has a floating gate transistor as a corresponding capacitor 失效用于具有浮置晶体管作为相应电容器的电容分压器中的电容器公开(公告)号：US06262469B1
公开(公告)日：2001-07-17
申请号：US09047237
申请日：1998-03-25
IPC分类号： H01L2900
CPC分类号： H01L29/94 , H01L27/0811 , H01L29/66189
摘要： A capacitor divider includes two capacitors coupled in series between two voltage sources. A first capacitor is a floating gate capacitor having one plate being the control gate of a floating gate transistor structure and the other plate being a source, drain, and channel region of the floating gate transistor structure. The capacitive divider has the advantage of having at least one floating gate capacitor, can be implemented in a voltage regulator, and works for a variety of voltages across the capacitors.
摘要翻译： 电容器分压器包括两个电容器，它们串联在两个电压源之间。 第一电容器是浮置栅极电容器，其中一个板是浮栅晶体管结构的控制栅极，另一个栅极是浮栅晶体管结构的源极，漏极和沟道区。 电容分压器的优点是具有至少一个浮置栅极电容器，可以在电压调节器中实现，并且可以用于跨越电容器的各种电压。
-
5.发明授权Dual source side polysilicon select gate structure and programming method utilizing single tunnel oxide for NAND array flash memory 失效双源多晶硅选择门结构和编程方法，利用单隧道氧化物进行NAND阵列闪存
公开(公告)号：US5999452A
公开(公告)日：1999-12-07
申请号：US63688
申请日：1998-04-21
申请人： Pau-Ling Chen , Mike Van Buskirk , Shane Charles Hollmer , Binh Quang Le , Shoichi Kawamura , Chung-You Hu , Yu Sun , Sameer Haddad , Chi Chang
发明人： Pau-Ling Chen , Mike Van Buskirk , Shane Charles Hollmer , Binh Quang Le , Shoichi Kawamura , Chung-You Hu , Yu Sun , Sameer Haddad , Chi Chang
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： G11C16/0483
摘要： A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.
摘要翻译： 串联选择晶体管和源选择晶体管串联连接在浮动数据存储晶体管的NAND串的末端。 浮置栅极，串联选择栅极和源选择栅极都优选由多晶硅形成。 相同的隧道氧化物层用作串联选择晶体管和源极选择晶体管以及浮动栅极数据存储晶体管的栅极氧化物。 串联选择栅极和源极选择栅极中的两层多晶硅结合在一起。 串联选择晶体管连接到NAND串中的最后一个晶体管。 源选择晶体管连接到阵列Vss电源。 为了在另一NAND单元的编程期间编程禁止特定NAND单元，串联选择晶体管的栅极升高到Vcc，同时源极选择晶体管的栅极保持接地。 串联的两个晶体管能够在NAND串的末端承受高得多的电压，而不会在串联或源极选择晶体管中产生门极二极管结或氧化物击穿。
-
6.发明授权Dual source side polysilicon select gate structure utilizing single tunnel oxide for NAND array flash memory 失效双源端多晶硅选择门结构利用单隧道氧化物用于NAND阵列闪存
公开(公告)号：US5912489A
公开(公告)日：1999-06-15
申请号：US940674
申请日：1997-09-30
申请人： Pau-Ling Chen , Mike Van Buskirk , Shane Charles Hollmer , Binh Quang Le , Shoichi Kawamura , Chung-You Hu , Yu Sun , Sameer Haddad , Chi Chang
发明人： Pau-Ling Chen , Mike Van Buskirk , Shane Charles Hollmer , Binh Quang Le , Shoichi Kawamura , Chung-You Hu , Yu Sun , Sameer Haddad , Chi Chang
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0483
摘要： A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.
摘要翻译： 串联选择晶体管和源选择晶体管串联连接在浮动数据存储晶体管的NAND串的末端。 浮置栅极，串联选择栅极和源选择栅极都优选由多晶硅形成。 相同的隧道氧化物层用作串联选择晶体管和源极选择晶体管以及浮动栅极数据存储晶体管的栅极氧化物。 串联选择栅极和源极选择栅极中的两层多晶硅结合在一起。 串联选择晶体管连接到NAND串中的最后一个晶体管。 源选择晶体管连接到阵列Vss电源。 为了在另一NAND单元的编程期间编程禁止特定NAND单元，串联选择晶体管的栅极升高到Vcc，同时源极选择晶体管的栅极保持接地。 串联的两个晶体管能够在NAND串的末端承受高得多的电压，而不会在串联或源极选择晶体管中产生门极二极管结或氧化物击穿。
-
公开(公告)号：US06072725A
公开(公告)日：2000-06-06
申请号：US237257
申请日：1999-01-26
CPC分类号： G11C5/147
摘要： A method and an apparatus are provided for the production and supply of an erase voltage for the initial erasing operation of a floating gate transistor used as a capacitor in a voltage regulator, along with the proper electrical connection of the capacitor's control gate and commonly connected regions. In one embodiment, a capacitor erase control circuit controls a pass transistor for connecting the control gate of the floating gate capacitor to ground and another pass transistor for isolating the commonly connected source, drain and channel regions of the floating gate capacitor (the "well node") from ground. The erase control circuit simultaneously applies a capacitor erase input and a clock input to an erase voltage pass circuit to control a third pass transistor to apply an erase voltage to the well node, thereby erasing the floating gate capacitor. The erase control circuit and erase voltage pass circuit are formed on the same semiconductor substrate as the floating gate capacitor and the other components of the voltage regulator. The erasing methodology and apparatus enables economical implementation of an improved voltage regulator using a floating gate transistor.
摘要翻译： 提供了一种方法和装置，用于生产和提供用于在电压调节器中用作电容器的浮栅晶体管的初始擦除操作的擦除电压以及电容器的控制栅极和公共连接区域的适当电连接 。 在一个实施例中，电容器擦除控制电路控制用于将浮栅电容器的控制栅极连接到地的通过晶体管和用于隔离浮置栅极电容器（“阱节点”）的公共连接的源极，漏极和沟道区域的另一个通过晶体管 “）从地面。 擦除控制电路同时向擦除电压通过电路施加电容器擦除输入和时钟输入，以控制第三传输晶体管，以向阱节点施加擦除电压，从而擦除浮置栅极电容器。 擦除控制电路和擦除电压通过电路形成在与浮置栅极电容器和电压调节器的其它部件相同的半导体衬底上。 擦除方法和装置能够经济地实现使用浮栅晶体管的改进的稳压器。
-
8.发明授权Fast high voltage NMOS pass gate for integrated circuit with high voltage generator 失效具有高压发生器的集成电路的快速高压NMOS通道
公开(公告)号：US5939928A
公开(公告)日：1999-08-17
申请号：US914196
申请日：1997-08-19
摘要： In a high voltage pass gate suitable for use as a block decoder in a flash memory circuit, the boosting of the block decoder's internal nodes is performed using coupling capacitors and boost transistors which are decoupled from the high capacitance pass gate node. The block decoder uses three internal block decoder nodes. Each of the three nodes is held to ground by a corresponding discharge transistor when the block is unselected. Each of the three nodes of a selected block is discharged to a normal supply voltage by a corresponding diode-connected regulation transistor when the high voltage supply is turned off after a programming operation has finished. Each of the three nodes has a separate coupling capacitor associated with it. One of the nodes is connected to the gates of the high voltage pass transistors, this node has high capacitance. The remaining two nodes have relatively small coupling capacitors. These other two nodes are capacitively coupling during opposite phases of a clock, and one of them controls a boost transistor which charges the high capacitance pass gate node. Two embodiments are presented, one having one less transistor than the other.
摘要翻译： 在适用于闪速存储器电路中的块解码器的高压通道中，使用从高电容通过栅极节点去耦的耦合电容器和升压晶体管来执行块解码器的内部节点的升压。 块解码器使用三个内部块解码器节点。 当块未被选择时，三个节点中的每一个被相应的放电晶体管保持接地。 当编程操作完成后，当高压电源关闭时，所选块的三个节点中的每一个都通过相应的二极管连接的调节晶体管放电到正常的电源电压。 三个节点中的每一个具有与其相关联的单独的耦合电容器。 节点中的一个连接到高电压通过晶体管的栅极，该节点具有高电容。 剩余的两个节点具有相对较小的耦合电容器。 这些另外两个节点在时钟的相反相位期间电容耦合，并且其中一个节点控制对高电容通过门节点充电的升压晶体管。 呈现了两个实施例，一个具有比另一个更少的晶体管。
-
9.发明授权Dual source side polysilicon select gate structure and programming method utilizing single tunnel oxide for nand array flash memory 有权双源多晶硅选择门结构和编程方法，利用单隧道氧化物进行阵列闪存存储公开(公告)号：US06266275B1
公开(公告)日：2001-07-24
申请号：US09410512
申请日：1999-09-30
申请人： Paul-Ling Chen , Mike Van Buskirk , Shane Charles Hollmer , Binh Quang Le , Shoichi Kawamura , Chung-You Hu , Yu Sun , Sameer Haddad , Chi Chang
发明人： Paul-Ling Chen , Mike Van Buskirk , Shane Charles Hollmer , Binh Quang Le , Shoichi Kawamura , Chung-You Hu , Yu Sun , Sameer Haddad , Chi Chang
IPC分类号： G11C700
CPC分类号： G11C16/0483
摘要： A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.
摘要翻译： 串联选择晶体管和源选择晶体管串联连接在浮动数据存储晶体管的NAND串的末端。 浮置栅极，串联选择栅极和源选择栅极都优选由多晶硅形成。 相同的隧道氧化物层用作串联选择晶体管和源极选择晶体管以及浮动栅极数据存储晶体管的栅极氧化物。 串联选择栅极和源极选择栅极中的两层多晶硅结合在一起。 串联选择晶体管连接到NAND串中的最后一个晶体管。 源选择晶体管连接到阵列Vss电源。 为了在另一NAND单元的编程期间编程禁止特定NAND单元，串联选择晶体管的栅极升高到Vcc，同时源极选择晶体管的栅极保持接地。 串联的两个晶体管能够在NAND串的末端承受高得多的电压，而不会在串联或源极选择晶体管中产生门极二极管结或氧化物击穿。
-
公开(公告)号：US06791880B1
公开(公告)日：2004-09-14
申请号：US10431320
申请日：2003-05-06
IPC分类号： G11C1606
CPC分类号： G11C29/026 , G11C16/04 , G11C16/349 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C2029/5006
摘要： A non-volatile memory read circuit having adjustable current sources to provide end of life simulation. A flash memory device comprising a reference current source used to provide a reference current for comparison to the current of a memory cell being read, includes an adjustable current source in parallel with the memory cell being read, and an adjustable current source in parallel with the reference current source. The current from the memory cell, reference current source, and their parallel adjustable current sources are input to cascode circuits for conversion to voltages that are compared by a sense amplifier. The behavior of the cascode circuits and sense amplifier in response to changes in the memory cell and reference current source may be evaluated by adjusting the adjustable current sources so that the combined current at each input to the sense amplifier simulates the current of the circuit after aging or cycling.
摘要翻译： 具有可调节电流源以提供寿命终止模拟的非易失性存储器读取电路。 包括用于提供用于与正在读取的存储器单元的电流进行比较的参考电流的参考电流源的闪速存储器件包括与被读取的存储器单元并联的可调电流源，以及与可读电流源并联的可调电流源 参考电流源。 来自存储单元，参考电流源及其并联可调电流源的电流被输入到共源共栅电路，用于转换成由读出放大器比较的电压。 可以通过调节可调电流源来评估级联电路和读出放大器响应于存储器单元和参考电流源的变化的行为，使得在读出放大器的每个输入处的组合电流在老化之后模拟电路的电流 或骑自行车。
-
-
-
-
-
-
-
-
-
搜索结果
37 条记录 (耗时 0.029 秒)