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公开(公告)号：US20120044372A1
公开(公告)日：2012-02-23
申请号：US12858922
申请日：2010-08-18
CPC分类号： H04N5/232 , H04N5/2258 , H04N5/23245
摘要： Various techniques are provided for processing image data acquired using a digital image sensor. In accordance with aspects of the present disclosure, one such technique may relate to the processing of image data in a system that supports multiple image sensors. In one embodiment, the image processing system may include control circuitry configured to determine whether a device is operating in a single sensor mode (one active sensor) or a dual sensor mode (two active sensors). When operating in the single sensor mode, data may be provided directly to a front-end pixel processing unit from the sensor interface of the active sensor. When operating in a dual sensor mode, the image frames from the first and second sensors are provided to the front-end pixel processing unit in an interleaved manner. For instance, in one embodiment, the image frames from the first and second sensors are written to a memory, and then read out to the front-end pixel processing unit in an interleaved manner.
摘要翻译： 提供了用于处理使用数字图像传感器获取的图像数据的各种技术。 根据本公开的方面，一种这样的技术可以涉及在支持多个图像传感器的系统中对图像数据的处理。 在一个实施例中，图像处理系统可以包括被配置为确定设备是以单个传感器模式（一个有源传感器）或双传感器模式（两个有源传感器）操作的控制电路。 当在单传感器模式下操作时，数据可以从有源传感器的传感器接口直接提供给前端像素处理单元。 当以双传感器模式操作时，来自第一和第二传感器的图像帧以交错的方式提供给前端像素处理单元。 例如，在一个实施例中，来自第一和第二传感器的图像帧被写入存储器，然后以交错的方式读出到前端像素处理单元。
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公开(公告)号：US07984317B2
公开(公告)日：2011-07-19
申请号：US12053807
申请日：2008-03-24
IPC分类号： G06F1/28
CPC分类号： G06F1/30 , G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A system and method is disclosed for efficiently managing power distribution among the various functional blocks used within portable electronic devices. The method includes allowing each functional block to be independently controlled, containing its own low-level software and power controls for setting the local power state of the functional block. For each power control domain in the implementation, hardware uses these local power states and sets the actual operating state of the power control domain accordingly.
摘要翻译： 公开了一种用于在便携式电子设备中使用的各种功能块之间有效管理功率分配的系统和方法。 该方法包括允许每个功能块被独立控制，包含其自己的低级软件和用于设置功能块的本地功率状态的功率控制。 对于实现中的每个功率控制域，硬件使用这些本地电源状态，并相应地设置功率控制域的实际工作状态。
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公开(公告)号：US20090240959A1
公开(公告)日：2009-09-24
申请号：US12053807
申请日：2008-03-24
IPC分类号： G06F1/00
CPC分类号： G06F1/30 , G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A system and method is disclosed for efficiently managing power distribution among the various functional blocks used within portable electronic devices. The method includes allowing each functional block to be independently controlled, containing its own low-level software and power controls for setting the local power state of the functional block. For each power control domain in the implementation, hardware uses these local power states and sets the actual operating state of the power control domain accordingly.
摘要翻译： 公开了一种用于在便携式电子设备中使用的各种功能块之间有效管理功率分配的系统和方法。 该方法包括允许每个功能块被独立控制，包含其自己的低级软件和用于设置功能块的本地功率状态的功率控制。 对于实现中的每个功率控制域，硬件使用这些本地电源状态，并相应地设置功率控制域的实际工作状态。
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公开(公告)号：US07558947B1
公开(公告)日：2009-07-07
申请号：US10038431
申请日：2001-12-31
IPC分类号： G06F7/38
CPC分类号： G06F7/544 , G06F2207/5442
摘要： Methods and apparatuses for computing an absolute difference of two vectors of numbers. In one aspect of the invention, a method for execution by a microprocessor in response to receiving a single instruction includes: receiving a first plurality of numbers and a second plurality of numbers; and generating simultaneously a third plurality of numbers, each of which is an absolute difference between a number in the first plurality of numbers and a number in the second plurality of numbers. The above operations are performed in response to the microprocessor receiving the single instruction.
摘要翻译： 用于计算两个数字向量的绝对差的方法和装置。 在本发明的一个方面中，微处理器响应于接收单个指令而执行的方法包括：接收第一多个数字和第二多个数字; 并且同时产生第三多个数字，每个数字是第一多个数字中的数字和第二个多个数字中的数字之间的绝对差。 响应于微处理器接收到单个指令执行上述操作。
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公开(公告)号：US09332239B2
公开(公告)日：2016-05-03
申请号：US13484814
申请日：2012-05-31
申请人： Guy Cote , Sheng Lin , Suk Hwan Lim , D. Amnon Silverstein , Steven David Hordley , Joseph P. Bratt
发明人： Guy Cote , Sheng Lin , Suk Hwan Lim , D. Amnon Silverstein , Steven David Hordley , Joseph P. Bratt
CPC分类号： H04N9/646 , G06T1/20 , G06T3/4015 , G06T5/002 , G06T5/009 , G06T5/20 , G06T2207/10024 , H04N5/365 , H04N9/045 , H04N9/735
摘要： Systems and methods for processing image data in RGB format are provided. In one example, an electronic device includes memory to store image data in raw or RGB format, or both, and an RGB image processing pipeline to process the image data. Specifically, the RGB image processing pipeline may process the image data regardless of whether the image data is of raw or RGB format. The RGB image processing pipeline may include receiving logic to receive the image data in raw or RGB format and demosaicing logic to, when the receiving logic receives the image data in raw format, convert the image data into RGB format. The logic may include local tone mapping logic configured to apply spatially varying tone curves to the image data, a color correction matrix configured to correct color in the image data, and gamma logic configured to transform the image data into gamma space.
摘要翻译： 提供了以RGB格式处理图像数据的系统和方法。 在一个示例中，电子设备包括用于以原始或RGB格式或两者存储图像数据的存储器和用于处理图像数据的RGB图像处理流水线。 具体而言，RGB图像处理流水线可以处理图像数据，而不管图像数据是原始还是RGB格式。 RGB图像处理流水线可以包括接收逻辑以接收原始或RGB格式的图像数据和去马赛克逻辑，当接收逻辑以原始格式接收图像数据时，将图像数据转换为RGB格式。 逻辑可以包括被配置为将空间变化的色调曲线应用于图像数据的本地色调映射逻辑，配置为校正图像数据中的颜色的色彩校正矩阵，以及被配置为将图像数据变换为伽马空间的伽马逻辑。
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公开(公告)号：US08717391B2
公开(公告)日：2014-05-06
申请号：US12950267
申请日：2010-11-19
申请人： Joseph P. Bratt , Peter F. Holland
发明人： Joseph P. Bratt , Peter F. Holland
摘要： A display pipe may include fetch circuitry and a scaler unit, and registers programmable with information that defines active regions of an image frame. Pixels within the active regions are active pixels to be displayed, pixels outside of the active regions are inactive pixels not to be displayed. The fetch circuitry may retrieve frames from memory, retrieving the active pixels and not retrieving the inactive pixels as defined by the programmed contents of the registers. A scaler unit may produce scaled pixels from the fetched pixels, basing each scaled pixel on a respective corresponding set of pixels. When a given pixel of the respective corresponding set of pixels is an inactive pixel, the scaler unit may assign an estimated value to the given pixel based on one or more active pixels in the respective corresponding set of pixels. The scaler unit may provide the scaled pixels to a blend unit for blending with other pixels.
摘要翻译： 显示管可以包括提取电路和缩放器单元，并且可以用定义图像帧的有效区域的信息来编程。 活动区域内的像素是要显示的活动像素，活动区域之外的像素是不显示的不活动像素。 提取电路可以从存储器检索帧，检索有效像素，而不检索由寄存器的编程内容定义的非活动像素。 缩放器单元可以从获取的像素产生缩放的像素，将每个缩放的像素基于相应的相应的像素集。 当相应的相应像素集合的给定像素是非活动像素时，缩放器单元可以基于相应的相应像素集合中的一个或多个有效像素来分配给定像素的估计值。 缩放器单元可以将缩放的像素提供给用于与其他像素混合的混合单元。
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公开(公告)号：US20130322746A1
公开(公告)日：2013-12-05
申请号：US13484926
申请日：2012-05-31
申请人： Guy Cote , Sheng Lin , Suk Hwan Lim , D. Amnon Silverstein , Simon Wolfenden Butler , Mark A. Zimmer , Joseph P. Bratt
发明人： Guy Cote , Sheng Lin , Suk Hwan Lim , D. Amnon Silverstein , Simon Wolfenden Butler , Mark A. Zimmer , Joseph P. Bratt
IPC分类号： G06K9/40
CPC分类号： G06T1/20 , G06T3/4015
摘要： Systems and methods for processing YCC image data provided. In one example, an electronic device includes memory to store image data in RGB or YCC format and a YCC image processing pipeline to process the image data. The YCC image processing pipeline may include receiving logic configured to receive the image data in RGB or YCC format and color space conversion logic configured to, when the image data is received in RGB format, convert the image data into YCC format. The YCC image processing logic may also include luma sharpening and chroma suppression logic; brightness, contrast, and color adjustment logic; gamma logic; chroma decimation logic; scaling logic; and chromanoise reduction logic.
摘要翻译： 用于处理提供的YCC图像数据的系统和方法。 在一个示例中，电子设备包括以RGB或YCC格式存储图像数据的存储器和用于处理图像数据的YCC图像处理流水线。 YCC图像处理流水线可以包括被配置为接收RGB或YCC格式的图像数据的接收逻辑，以及配置为当以RGB格式接收图像数据时将图像数据转换为YCC格式的颜色空间转换逻辑。 YCC图像处理逻辑还可以包括亮度锐化和色度抑制逻辑; 亮度，对比度和颜色调整逻辑; 伽玛逻辑; 色度抽取逻辑; 缩放逻辑; 和色度降低逻辑。
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公开(公告)号：US20130322745A1
公开(公告)日：2013-12-05
申请号：US13484741
申请日：2012-05-31
申请人： Suk Hwan Lim , D. Amnon Silverstein , Guy Cote , Steven David Hordley , Graham Finlayson , Weichun Ku , Joseph P. Bratt
发明人： Suk Hwan Lim , D. Amnon Silverstein , Guy Cote , Steven David Hordley , Graham Finlayson , Weichun Ku , Joseph P. Bratt
IPC分类号： G06K9/36
CPC分类号： H04N9/73 , H04N5/142 , H04N9/045 , H04N9/735 , H04N2209/046
摘要： Systems and methods for generating local image statistics are provided. In one example, an image signal processing system may include a statistics pipeline with image processing logic and local image statistics collection logic. The image processing logic may receive and process pixels of raw image data. The local image statistics collection logic may generate a local histogram associated with a luminance of the pixels of a first block of pixels of the raw image data or a thumbnail in which a pixel of the thumbnail represents a downscaled version of the luminance of the pixels of the first block of the pixel. The raw image data may include many other blocks of pixels of the same size as the first block of pixels.
摘要翻译： 提供了生成本地图像统计信息的系统和方法。 在一个示例中，图像信号处理系统可以包括具有图像处理逻辑和本地图像统计信息收集逻辑的统计流水线。 图像处理逻辑可以接收和处理原始图像数据的像素。 本地图像统计收集逻辑可以生成与原始图像数据的第一像素块的像素的亮度相关联的局部直方图或缩略图，其中缩略图的像素表示缩略图的像素的亮度 像素的第一个块。 原始图像数据可以包括与第一像素块相同尺寸的许多其他像素块。
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19.发明授权Image signal processor line buffer configuration for processing ram image data 有权用于处理原始图像数据的图像信号处理器线缓冲器配置公开(公告)号：US08508612B2
公开(公告)日：2013-08-13
申请号：US12895396
申请日：2010-09-30
IPC分类号： H04N5/228
CPC分类号： H04N9/045 , G06T3/4015
摘要： The present disclosure provides techniques relates to the implementation of a raw pixel processing unit using a set of line buffers. In one embodiment, the set of line buffers may include a first subset and second subset. Various logical units of the raw pixel processing unit may be implemented using the first and second subsets of line buffers in a shared manner. For instance, in one embodiment, defective pixel correction and detection logic may be implemented using the first subset of line buffers. The second subset of line buffers may be used to implement lens shading correction logic, gain, offset, and clamping logic, and demosaicing logic. Further, noise reduction may also be implemented using at least a portion of each of the first and second subsets of line buffers.
摘要翻译： 本公开提供了技术涉及使用一组行缓冲器的原始像素处理单元的实现。 在一个实施例中，行缓冲器组可以包括第一子集和第二子集。 可以以共享的方式使用第一和第二子行的行缓冲器来实现原始像素处理单元的各种逻辑单元。 例如，在一个实施例中，可以使用线缓冲器的第一子集来实现有缺陷的像素校正和检测逻辑。 行缓冲器的第二子集可用于实现镜头阴影校正逻辑，增益，偏移和钳位逻辑以及去马赛克逻辑。 此外，还可以使用行缓冲器的第一和第二子集中的每一个的至少一部分来实现噪声降低。
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公开(公告)号：US20120151104A1
公开(公告)日：2012-06-14
申请号：US12966946
申请日：2010-12-13
申请人： Joseph P. Bratt , Lakshmi Rao
发明人： Joseph P. Bratt , Lakshmi Rao
CPC分类号： G06F13/28
摘要： Techniques are disclosed relating to detecting and interjecting a programmed input/output (PIO) operation into a direct memory access (DMA) operation. In one embodiment, an integrated circuit may include a DMA controller that may contain a control circuit, a DMA unit, and a PIO unit. The control circuit may be configured to detect a pending PIO operation during a DMA operation and interject the PIO operation onto a shared path during the same clock cycle as or the first clock cycle following the detection of the pending PIO operation. The DMA operation may consist of multiple single-clock-cycle beats. In one embodiment, a PIO operation may be interjected onto the shared path between beats of a DMA operation, on consecutive clock cycles. At the next clock cycle following the PIO operation, the control circuit may resume the next beat of the DMA operation.
摘要翻译： 公开了关于将编程的输入/输出（PIO）操作检测和插入到直接存储器访问（DMA）操作中的技术。 在一个实施例中，集成电路可以包括可以包含控制电路，DMA单元和PIO单元的DMA控制器。 控制电路可以被配置为在DMA操作期间检测待处理的PIO操作，并且在与待处理的PIO操作的检测之后的相同时钟周期期间或在第一时钟周期之后将PIO操作插入到共享路径上。 DMA操作可以由多个单时钟周期节拍组成。 在一个实施例中，可以在连续的时钟周期上将PIO操作插入在DMA操作的节拍之间的共享路径上。 在PIO操作之后的下一个时钟周期，控制电路可以恢复DMA操作的下一个节拍。
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