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公开(公告)号：US07984317B2
公开(公告)日：2011-07-19
申请号：US12053807
申请日：2008-03-24
IPC分类号： G06F1/28
CPC分类号： G06F1/30 , G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A system and method is disclosed for efficiently managing power distribution among the various functional blocks used within portable electronic devices. The method includes allowing each functional block to be independently controlled, containing its own low-level software and power controls for setting the local power state of the functional block. For each power control domain in the implementation, hardware uses these local power states and sets the actual operating state of the power control domain accordingly.
摘要翻译： 公开了一种用于在便携式电子设备中使用的各种功能块之间有效管理功率分配的系统和方法。 该方法包括允许每个功能块被独立控制，包含其自己的低级软件和用于设置功能块的本地功率状态的功率控制。 对于实现中的每个功率控制域，硬件使用这些本地电源状态，并相应地设置功率控制域的实际工作状态。
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公开(公告)号：US20090240959A1
公开(公告)日：2009-09-24
申请号：US12053807
申请日：2008-03-24
IPC分类号： G06F1/00
CPC分类号： G06F1/30 , G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A system and method is disclosed for efficiently managing power distribution among the various functional blocks used within portable electronic devices. The method includes allowing each functional block to be independently controlled, containing its own low-level software and power controls for setting the local power state of the functional block. For each power control domain in the implementation, hardware uses these local power states and sets the actual operating state of the power control domain accordingly.
摘要翻译： 公开了一种用于在便携式电子设备中使用的各种功能块之间有效管理功率分配的系统和方法。 该方法包括允许每个功能块被独立控制，包含其自己的低级软件和用于设置功能块的本地功率状态的功率控制。 对于实现中的每个功率控制域，硬件使用这些本地电源状态，并相应地设置功率控制域的实际工作状态。
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公开(公告)号：US09032113B2
公开(公告)日：2015-05-12
申请号：US12057146
申请日：2008-03-27
CPC分类号： G06F13/34 , G06F1/12 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F1/3287 , G06F13/1673 , G06F13/28 , Y02D10/126 , Y02D10/151 , Y02D10/171
摘要： A method and system is disclosed for accessing I/O and memory devices utilizing a DMA controller. Each device may be connected to the DMA controller through an individual channel. Clocking circuitry in the DMA may allow the DMA controller to send signals to each device at a prescribed frequency. Furthermore, the DMA controller is capable of activating and deactivating a channel clock, used in sending signals to the devices, based on the operational status of the individual devices. The DMA controller is also capable of tuning the channel clock dependant on the capabilities of any active devices. In this manner, the amount of bandwidth used during a DMA data transfer can be tailored to the specific requirements of the devices involved with the data transfer.
摘要翻译： 公开了一种利用DMA控制器访问I / O和存储器件的方法和系统。 每个设备可以通过单独的通道连接到DMA控制器。 DMA中的时钟电路可以允许DMA控制器以规定的频率向每个设备发送信号。 此外，DMA控制器能够基于各个设备的操作状态来激活和去激活用于向设备发送信号的通道时钟。 DMA控制器还能够根据任何有源器件的功能调整通道时钟。 以这种方式，DMA数据传输期间使用的带宽量可以根据与数据传输相关的设备的具体要求进行调整。
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公开(公告)号：US20110246806A1
公开(公告)日：2011-10-06
申请号：US13160234
申请日：2011-06-14
IPC分类号： G06F1/28
CPC分类号： G06F1/30 , G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A system and method is disclosed for efficiently managing power distribution among the various functional blocks used within portable electronic devices. The method includes allowing each functional block to be independently controlled, containing its own low-level software and power controls for setting the local power state of the functional block. For each power control domain in the implementation, hardware uses these local power states and determines and sets the actual operating state of the power control domain accordingly.
摘要翻译： 公开了一种用于在便携式电子设备中使用的各种功能块之间有效管理功率分配的系统和方法。 该方法包括允许每个功能块被独立控制，包含其自己的低级软件和用于设置功能块的本地功率状态的功率控制。 对于实施中的每个功率控制域，硬件使用这些本地电源状态，并相应地确定和设置功率控制域的实际工作状态。
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公开(公告)号：US20090248911A1
公开(公告)日：2009-10-01
申请号：US12057146
申请日：2008-03-27
IPC分类号： G06F1/12
CPC分类号： G06F13/34 , G06F1/12 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F1/3287 , G06F13/1673 , G06F13/28 , Y02D10/126 , Y02D10/151 , Y02D10/171
摘要： A method and system is disclosed for accessing I/O and memory devices utilizing a DMA controller. Each device may be connected to the DMA controller through an individual channel. Clocking circuitry in the DMA may allow the DMA controller to send signals to each device at a prescribed frequency. Furthermore, the DMA controller is capable of activating and deactivating a channel clock, used in sending signals to the devices, based on the operational status of the individual devices. The DMA controller is also capable of tuning the channel clock dependant on the capabilities of any active devices. In this manner, the amount of bandwidth used during a DMA data transfer can be tailored to the specific requirements of the devices involved with the data transfer.
摘要翻译： 公开了一种利用DMA控制器访问I / O和存储器件的方法和系统。 每个设备可以通过单独的通道连接到DMA控制器。 DMA中的时钟电路可以允许DMA控制器以规定的频率向每个设备发送信号。 此外，DMA控制器能够基于各个设备的操作状态来激活和去激活用于向设备发送信号的通道时钟。 DMA控制器还能够根据任何有源器件的功能调整通道时钟。 以这种方式，DMA数据传输期间使用的带宽量可以根据与数据传输相关的设备的具体要求进行调整。
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公开(公告)号：US08749568B2
公开(公告)日：2014-06-10
申请号：US12685166
申请日：2010-01-11
IPC分类号： G09G5/36
CPC分类号： G06T1/60 , G09G5/14 , G09G5/363 , G09G2340/10 , G09G2360/12 , G09G2360/127
摘要： A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve and process a top frame packet from the parameter buffer to update one or more of the parameter registers according to the contents of the top frame packet. The control circuit may issue DMA requests to fill the parameter buffer with frame packets transferred from system memory, where the frame packets may be written by an application (or software) executing on a central processing unit.
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公开(公告)号：US08493482B2
公开(公告)日：2013-07-23
申请号：US12858922
申请日：2010-08-18
IPC分类号： H04N3/14 , H04N5/335 , H01L31/062
CPC分类号： H04N5/232 , H04N5/2258 , H04N5/23245
摘要： Various techniques are provided for processing image data acquired using a digital image sensor. In accordance with aspects of the present disclosure, one such technique may relate to the processing of image data in a system that supports multiple image sensors. In one embodiment, the image processing system may include control circuitry configured to determine whether a device is operating in a single sensor mode (one active sensor) or a dual sensor mode (two active sensors). When operating in the single sensor mode, data may be provided directly to a front-end pixel processing unit from the sensor interface of the active sensor. When operating in a dual sensor mode, the image frames from the first and second sensors are provided to the front-end pixel processing unit in an interleaved manner. For instance, in one embodiment, the image frames from the first and second sensors are written to a memory, and then read out to the front-end pixel processing unit in an interleaved manner.
摘要翻译： 提供了用于处理使用数字图像传感器获取的图像数据的各种技术。 根据本公开的方面，一种这样的技术可以涉及在支持多个图像传感器的系统中对图像数据的处理。 在一个实施例中，图像处理系统可以包括被配置为确定设备是以单个传感器模式（一个有源传感器）或双传感器模式（两个有源传感器）操作的控制电路。 当在单传感器模式下操作时，数据可以从有源传感器的传感器接口直接提供给前端像素处理单元。 当以双传感器模式操作时，来自第一和第二传感器的图像帧以交错的方式提供给前端像素处理单元。 例如，在一个实施例中，来自第一和第二传感器的图像帧被写入存储器，然后以交错的方式读出到前端像素处理单元。
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公开(公告)号：US20120044372A1
公开(公告)日：2012-02-23
申请号：US12858922
申请日：2010-08-18
CPC分类号： H04N5/232 , H04N5/2258 , H04N5/23245
摘要： Various techniques are provided for processing image data acquired using a digital image sensor. In accordance with aspects of the present disclosure, one such technique may relate to the processing of image data in a system that supports multiple image sensors. In one embodiment, the image processing system may include control circuitry configured to determine whether a device is operating in a single sensor mode (one active sensor) or a dual sensor mode (two active sensors). When operating in the single sensor mode, data may be provided directly to a front-end pixel processing unit from the sensor interface of the active sensor. When operating in a dual sensor mode, the image frames from the first and second sensors are provided to the front-end pixel processing unit in an interleaved manner. For instance, in one embodiment, the image frames from the first and second sensors are written to a memory, and then read out to the front-end pixel processing unit in an interleaved manner.
摘要翻译： 提供了用于处理使用数字图像传感器获取的图像数据的各种技术。 根据本公开的方面，一种这样的技术可以涉及在支持多个图像传感器的系统中对图像数据的处理。 在一个实施例中，图像处理系统可以包括被配置为确定设备是以单个传感器模式（一个有源传感器）或双传感器模式（两个有源传感器）操作的控制电路。 当在单传感器模式下操作时，数据可以从有源传感器的传感器接口直接提供给前端像素处理单元。 当以双传感器模式操作时，来自第一和第二传感器的图像帧以交错的方式提供给前端像素处理单元。 例如，在一个实施例中，来自第一和第二传感器的图像帧被写入存储器，然后以交错的方式读出到前端像素处理单元。
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公开(公告)号：US08669993B2
公开(公告)日：2014-03-11
申请号：US12685152
申请日：2010-01-11
CPC分类号： G06F3/14 , G09G5/14 , G09G5/397 , G09G2340/10 , G09G2360/12
摘要： A user interface unit in a graphics processing display pipe may include registers programmable with information that defines active regions of an image frame. Pixels within the active regions of the image frame are meant to be displayed, while pixels outside of the active regions of the image frame are not to be displayed. Fetch circuitry within the user interface unit may fetch frames from memory, fetching only the pixels within the active regions of the image frames as defined by the programmed contents of the registers. The user interface unit may then provide the fetched pixels to a blend unit to blend the fetched pixels with pixels from other frames or pixels of a video stream to produce output frames. When blended with pixels of a video stream, the fetched pixels may be displayed as a graphics overlay on top of the video stream.
摘要翻译： 图形处理显示管道中的用户界面单元可以包括可以定义图像帧的有效区域的信息来编程的寄存器。 旨在显示图像帧的有效区域内的像素，而不显示图像帧的有效区域之外的像素。 用户接口单元内的提取电路可以从存储器获取帧，仅获取由寄存器的编程内容定义的图像帧的有效区域内的像素。 然后，用户界面单元可以将获取的像素提供给混合单元，以将获取的像素与来自视频流的其他帧或像素的像素混合以产生输出帧。 当与视频流的像素混合时，获取的像素可以被显示为视频流顶部的图形覆盖。
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公开(公告)号：US08675004B2
公开(公告)日：2014-03-18
申请号：US12685171
申请日：2010-01-11
IPC分类号： G06F13/372
摘要： A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs. The underrun pixel may be supplied to the display controller until the underrun has been resolved, at which point the most recent valid pixel read from the buffer may be supplied to the display controller.
摘要翻译： 图形系统可以包括具有缓冲器的显示管道，缓冲器被配置为存储要由显示控制器处理的像素，用于在显示设备上显示，缓冲器控制电路耦合到缓冲器以向显示控制器提供像素。 当缓冲器控制电路响应于显示控制器尝试读取尚未写入缓冲器的缓冲器的像素时，缓冲器控制电路检测到欠载，缓冲器控制电路可以向显示器提供欠载像素。 欠载像素可以从先前存储的欠载像素组中选择，其可以包括由显示控制器读取的最新有效像素。 即使在出现欠载条件的情况下，代表显示控制器当前尝试读取的缓冲器中的位置的读取指针也可以被提前。 欠载像素可以被提供给显示控制器，直到欠载已被解析为止，此时从缓冲器读取的最新的有效像素可以被提供给显示控制器。
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