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    Controller and Fabric Performance Testing
    1.
    发明申请
    Controller and Fabric Performance Testing 失效
    控制器和织物性能测试

    公开(公告)号：US20120046930A1

    公开(公告)日：2012-02-23

    申请号：US12860668

    申请日：2010-08-20

    申请人： Marc A. Schaub ,  Shun Wai Go ,  Sukalpa Biswas ,  Timothy J. Millet

    发明人： Marc A. Schaub ,  Shun Wai Go ,  Sukalpa Biswas ,  Timothy J. Millet

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022

    摘要： In an embodiment, a model may be created using a register-transfer level (RTL) representation (or other cycle-accurate representation) of the controller and the circuitry in the communication fabric to the controller. The request sources may be replaced by transactors, which may generate transactions to test the performance of the fabric and controller. Accordingly, only the designs of the controller and the fabric circuitry may be needed to model performance in this embodiment. In an embodiment, at least some of the transactors may be behavioral transactors that attempt to mimic the operation of corresponding request sources. Other transactors may be statistical distributions, in some embodiments. In an embodiment, the transactors may include a transaction generator (e.g. behavioral or statistical) and a protocol translator configured to convert generated transactions to the communication protocol in use at the point that the transactor is connected to the fabric.

    摘要翻译： 在一个实施例中，可以使用控制器的寄存器传送级（RTL）表示（或其他周期精确表示）以及到控制器的通信结构中的电路来创建模型。 请求源可以被交易者代替，交易者可以生成事务来测试结构和控制器的性能。 因此，在该实施例中，仅需要控制器和结构电路的设计来建模性能。 在一个实施例中，至少一些事务者可以是尝试模拟相应请求源的操作的行为事务者。 在一些实施例中，其他交易者可以是统计分布。 在一个实施例中，事务处理器可以包括交易发生器（例如行为或统计）和协议转换器，其被配置为在交易者连接到该结构的点处将生成的交易转换为使用中的通信协议。

    Tracking a non-posted writes in a system using a storage location to store a write response indicator when the non-posted write has reached a target device
    2.
    发明授权
    Tracking a non-posted writes in a system using a storage location to store a write response indicator when the non-posted write has reached a target device 有权
    当非发布的写入已到达目标设备时，使用存储位置跟踪系统中的未发布的写入以存储写入响应指示符

    公开(公告)号：US07003615B2

    公开(公告)日：2006-02-21

    申请号：US10127130

    申请日：2002-04-22

    申请人： Kwong-Tak A. Chui ,  Shun Wai Go ,  Mark D. Hayter ,  Chun H. Ning ,  Amy K. Silveria

    发明人： Kwong-Tak A. Chui ,  Shun Wai Go ,  Mark D. Hayter ,  Chun H. Ning ,  Amy K. Silveria

    IPC分类号： G06F13/36

    CPC分类号： G06F13/4217

    摘要： An apparatus includes a storage location and a write monitor circuit coupled to the storage location. The storage location is configured to store a write response indicator which is capable of indicating a reception of at least one write response. Each write response indicates that a corresponding write has reached a target device of that write. The write monitor circuit is configured to update the write response indicator in response to receiving an indication of a first write response. A computer accessible medium may comprises instructions which, when executed: (i) initialize the write response indicator; and (ii) issue one or more writes to a target device, wherein the target device is configured to response to each of the writes with a write response to be indicated by the write response indicator.

    摘要翻译： 一种装置包括存储位置和耦合到存储位置的写监视器电路。 存储位置被配置为存储能够指示接收至少一个写入响应的写入响应指示符。 每个写入响应指示相应的写入已到达该写入的目标器件。 写入监视器电路被配置为响应于接收到第一写入响应的指示来更新写入响应指示符。 计算机可访问介质可以包括指令，当被执行时：（i）初始化写入响应指示符; 以及（ii）向目标设备发出一个或多个写入，其中所述目标设备被配置为响应于由所述写入响应指示符指示的写入响应。

    Dual image sensor image processing system and method
    6.
    发明授权
    Dual image sensor image processing system and method 有权
    双图像传感器图像处理系统及方法

    公开(公告)号：US08493482B2

    公开(公告)日：2013-07-23

    申请号：US12858922

    申请日：2010-08-18

    申请人： Guy Cote ,  Jeffrey E. Frederiksen ,  Joseph P. Bratt ,  Shun Wai Go ,  Timothy J. Millet

    发明人： Guy Cote ,  Jeffrey E. Frederiksen ,  Joseph P. Bratt ,  Shun Wai Go ,  Timothy J. Millet

    IPC分类号： H04N3/14 ,  H04N5/335 ,  H01L31/062

    CPC分类号： H04N5/232 ,  H04N5/2258 ,  H04N5/23245

    摘要： Various techniques are provided for processing image data acquired using a digital image sensor. In accordance with aspects of the present disclosure, one such technique may relate to the processing of image data in a system that supports multiple image sensors. In one embodiment, the image processing system may include control circuitry configured to determine whether a device is operating in a single sensor mode (one active sensor) or a dual sensor mode (two active sensors). When operating in the single sensor mode, data may be provided directly to a front-end pixel processing unit from the sensor interface of the active sensor. When operating in a dual sensor mode, the image frames from the first and second sensors are provided to the front-end pixel processing unit in an interleaved manner. For instance, in one embodiment, the image frames from the first and second sensors are written to a memory, and then read out to the front-end pixel processing unit in an interleaved manner.

    摘要翻译： 提供了用于处理使用数字图像传感器获取的图像数据的各种技术。 根据本公开的方面，一种这样的技术可以涉及在支持多个图像传感器的系统中对图像数据的处理。 在一个实施例中，图像处理系统可以包括被配置为确定设备是以单个传感器模式（一个有源传感器）或双传感器模式（两个有源传感器）操作的控制电路。 当在单传感器模式下操作时，数据可以从有源传感器的传感器接口直接提供给前端像素处理单元。 当以双传感器模式操作时，来自第一和第二传感器的图像帧以交错的方式提供给前端像素处理单元。 例如，在一个实施例中，来自第一和第二传感器的图像帧被写入存储器，然后以交错的方式读出到前端像素处理单元。

    DUAL IMAGE SENSOR IMAGE PROCESSING SYSTEM AND METHOD
    7.
    发明申请
    DUAL IMAGE SENSOR IMAGE PROCESSING SYSTEM AND METHOD 有权
    双图像传感器图像处理系统和方法

    公开(公告)号：US20120044372A1

    公开(公告)日：2012-02-23

    申请号：US12858922

    申请日：2010-08-18

    申请人： Guy Côté ,  Jeffrey E. Frederiksen ,  Joseph P. Bratt ,  Shun Wai Go ,  Timothy J. Millet

    发明人： Guy Côté ,  Jeffrey E. Frederiksen ,  Joseph P. Bratt ,  Shun Wai Go ,  Timothy J. Millet

    IPC分类号： H04N5/225 ,  H04N5/228

    CPC分类号： H04N5/232 ,  H04N5/2258 ,  H04N5/23245

    摘要： Various techniques are provided for processing image data acquired using a digital image sensor. In accordance with aspects of the present disclosure, one such technique may relate to the processing of image data in a system that supports multiple image sensors. In one embodiment, the image processing system may include control circuitry configured to determine whether a device is operating in a single sensor mode (one active sensor) or a dual sensor mode (two active sensors). When operating in the single sensor mode, data may be provided directly to a front-end pixel processing unit from the sensor interface of the active sensor. When operating in a dual sensor mode, the image frames from the first and second sensors are provided to the front-end pixel processing unit in an interleaved manner. For instance, in one embodiment, the image frames from the first and second sensors are written to a memory, and then read out to the front-end pixel processing unit in an interleaved manner.

    摘要翻译： 提供了用于处理使用数字图像传感器获取的图像数据的各种技术。 根据本公开的方面，一种这样的技术可以涉及在支持多个图像传感器的系统中对图像数据的处理。 在一个实施例中，图像处理系统可以包括被配置为确定设备是以单个传感器模式（一个有源传感器）或双传感器模式（两个有源传感器）操作的控制电路。 当在单传感器模式下操作时，数据可以从有源传感器的传感器接口直接提供给前端像素处理单元。 当以双传感器模式操作时，来自第一和第二传感器的图像帧以交错的方式提供给前端像素处理单元。 例如，在一个实施例中，来自第一和第二传感器的图像帧被写入存储器，然后以交错的方式读出到前端像素处理单元。

    Programmable inter-virtual channel and intra-virtual channel instructions issuing rules for an I/O bus of a system-on-a-chip processor
    9.
    发明授权
    Programmable inter-virtual channel and intra-virtual channel instructions issuing rules for an I/O bus of a system-on-a-chip processor 有权
    针对片上系统处理器的I / O总线的可编程虚拟间通道和虚拟通道指令发布规则

    公开(公告)号：US07240141B2

    公开(公告)日：2007-07-03

    申请号：US10821397

    申请日：2004-04-09

    申请人： Chun Hung Ning ,  Laurent Rene Moll ,  Kwong-Tak Chui ,  Shun Wai Go ,  Piyush Shashikant Jamkhandi

    发明人： Chun Hung Ning ,  Laurent Rene Moll ,  Kwong-Tak Chui ,  Shun Wai Go ,  Piyush Shashikant Jamkhandi

    IPC分类号： G06F13/366

    CPC分类号： G06F13/4031

    摘要： A method and apparatus for programming instruction issuing rules for instructions residing among various virtual channels, as well as the same virtual channel of an I/O bus interface for a system-on-a-chip processor. In the method and apparatus of the present invention both intra-virtual channel dependencies and inter-virtual channel dependencies are fully programmable, thereby offering significant advantages over prior art I/O interfaces. The method and apparatus of the present invention is broadly comprised of a system for managing data transactions between a first bus and a second bus. A first transaction conversion module is operably connected to the first bus and is operable to receive transactions from the first bus and a first format and to convert those transactions into an internal format. An ordering rules logic module is operably connected to the first transaction conversion module and is further operable to control issuing of transactions in accordance with a dependency relationship between the individual transactions. The ordering rules logic module generates validated transactions that are provided to a second conversion transaction module which is operably connected to the second bus. The ordering rules logic module of the present invention is fully programmable and, therefore, does not need to be redesigned when the data processing system is adapted to operate on a new bus system.

    摘要翻译： 一种方法和装置，用于编程驻留在各种虚拟信道之间的指令的指令发布规则，以及用于片上系统处理器的I / O总线接口的相同虚拟通道。 在本发明的方法和装置中，虚拟内信道依赖性和虚拟间信道依赖性都是完全可编程的，从而提供了优于现有技术I / O接口的显着优点。 本发明的方法和装置广泛地包括用于管理第一总线和第二总线之间的数据交易的系统。 第一交易转换模块可操作地连接到第一总线，并且可操作以从第一总线接收交易和第一格式，并将这些交易转换成内部格式。 排序规则逻辑模块可操作地连接到第一交易转换模块，并且还可操作以根据各个交易之间的依赖关系来控制交易的发行。 排序规则逻辑模块产生被提供给可操作地连接到第二总线的第二转换事务模块的验证事务。 本发明的排序规则逻辑模块是完全可编程的，因此，当数据处理系统适于在新总线系统上操作时，不需要重新设计。