公开(公告)号：US20080184064A1

公开(公告)日：2008-07-31

申请号：US11669667

申请日：2007-01-31

Applicant: Jui-Jen Wu ,  Yung-Lung Lin ,  Yen-Huei Chen ,  Dao-Ping Wang

Inventor： Jui-Jen Wu ,  Yung-Lung Lin ,  Yen-Huei Chen ,  Dao-Ping Wang

IPC: G06F11/16

CPC classification number: G11C29/808

Abstract: The disclosure generally relates to a method and apparatus for a high efficiency redundancy scheme for a memory system. In one embodiment, the disclosure relates to a memory circuit having: a memory array defined by a plurality of memory cells arranged in one or more columns and one or more rows, each memory cell communicating with one of a pair of complementary bit-lines and with a word-line; a plurality of IO circuits, each IO circuit associated with one of the plurality of memory cell columns; a plurality of redundant bit-lines, each redundant bit line communicating with a redundant bit cell; a first circuit for detecting a defective memory cell in said memory circuit; a second circuit for selecting one of the plurality of redundant bit-lines for switching from the failed memory cell to the redundant memory cell; and a third circuit for directing a word-line pulse of said defective memory cell to said selected redundant memory cell.

Abstract translation: 本公开一般涉及用于存储器系统的高效冗余方案的方法和装置。 在一个实施例中，本公开涉及一种存储器电路，其具有：由多个存储单元限定的存储器阵列，所述多个存储器单元被布置成一列或多列和一行或多行，每个存储器单元与一对互补位线中的一个通信， 用字线; 多个IO电路，与所述多个存储单元列之一相关联的每个IO电路; 多个冗余位线，每个冗余位线与冗余位单元通信; 用于检测所述存储器电路中的有缺陷的存储单元的第一电路; 用于选择所述多个冗余位线中的一个用于从所述故障存储器单元切换到所述冗余存储器单元的第二电路; 以及用于将所述有缺陷的存储器单元的字线脉冲引导到所述选择的冗余存储单元的第三电路。

公开(公告)号：US20070159231A1

公开(公告)日：2007-07-12

申请号：US11328780

申请日：2006-01-10

Applicant: Yung-Lung Lin ,  Jui-Jen Wu ,  Hung-Jen Liao

Inventor： Yung-Lung Lin ,  Jui-Jen Wu ,  Hung-Jen Liao

IPC: H01H37/76

CPC classification number: G11C11/56 ,  G11C17/18

Abstract: An integrated circuit for programming an electrical fuse includes a first programming device coupled to the electrical fuse for selectively providing the same with a first programming current, and a second programming device coupled to the electrical fuse for selectively providing the same with a second programming current. A detection module is coupled to the electrical fuse for generating an output indicating a resistance level of the electrical fuse, wherein the resistance level has three or more predetermined states, which are provided by selectively programming the electrical fuse with the first or second programming current.

公开(公告)号：US07505319B2

公开(公告)日：2009-03-17

申请号：US11669667

申请日：2007-01-31

Applicant: Jui-Jen Wu ,  Yung-Lung Lin ,  Yen-Huei Chen ,  Dao-Ping Wang

Inventor： Jui-Jen Wu ,  Yung-Lung Lin ,  Yen-Huei Chen ,  Dao-Ping Wang

IPC: G11C11/34

CPC classification number: G11C29/808

Abstract: The disclosure generally relates to a method and apparatus for a high efficiency redundancy scheme for a memory system. In one embodiment, the disclosure relates to a memory circuit having: a memory array defined by a plurality of memory cells arranged in one or more columns and one or more rows, each memory cell communicating with one of a pair of complementary bit-lines and with a word-line; a plurality of IO circuits, each IO circuit associated with one of the plurality of memory cell columns; a plurality of redundant bit-lines, each redundant bit line communicating with a redundant bit cell; a first circuit for detecting a defective memory cell in said memory circuit; a second circuit for selecting one of the plurality of redundant bit-lines for switching from the failed memory cell to the redundant memory cell; and a third circuit for directing a word-line pulse of said defective memory cell to said selected redundant memory cell.

Abstract translation: 本公开一般涉及用于存储器系统的高效冗余方案的方法和装置。 在一个实施例中，本公开涉及一种存储器电路，其具有：由多个存储单元限定的存储器阵列，所述多个存储器单元被布置成一列或多列和一行或多行，每个存储器单元与一对互补位线中的一个通信， 用字线; 多个IO电路，与所述多个存储单元列之一相关联的每个IO电路; 多个冗余位线，每个冗余位线与冗余位单元通信; 用于检测所述存储电路中的有缺陷的存储单元的第一电路; 用于选择所述多个冗余位线中的一个用于从所述故障存储器单元切换到所述冗余存储器单元的第二电路; 以及用于将所述有缺陷的存储器单元的字线脉冲引导到所述选择的冗余存储单元的第三电路。

公开(公告)号：US20080217734A1

公开(公告)日：2008-09-11

申请号：US11715631

申请日：2007-03-08

Applicant: Yung-Lung Lin ,  Jui-Jen Wu ,  Shine Chung ,  Fu-Lung Hsuen

Inventor： Yung-Lung Lin ,  Jui-Jen Wu ,  Shine Chung ,  Fu-Lung Hsuen

IPC: H01L29/00

CPC classification number: G11C11/5692 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-level electrical fuse system comprises at least one fuse box having at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.

Abstract translation: 多级电熔丝系统包括至少一个具有至少一个电熔丝的保险丝盒，串联耦合到电熔丝的编程装置，以及耦合到保险丝盒并被配置成产生两个或多个电压电平的可变电源。

公开(公告)号：US07271644B2

公开(公告)日：2007-09-18

申请号：US11328780

申请日：2006-01-10

Applicant: Yung-Lung Lin ,  Jui-Jen Wu ,  Hung-Jen Liao

Inventor： Yung-Lung Lin ,  Jui-Jen Wu ,  Hung-Jen Liao

IPC: H01H37/76 ,  H01H85/00

CPC classification number: G11C11/56 ,  G11C17/18

Abstract: An integrated circuit for programming an electrical fuse includes a first programming device coupled to the electrical fuse for selectively providing the same with a first programming current, and a second programming device coupled to the electrical fuse for selectively providing the same with a second programming current. A detection module is coupled to the electrical fuse for generating an output indicating a resistance level of the electrical fuse, wherein the resistance level has three or more predetermined states, which are provided by selectively programming the electrical fuse with the first or second programming current.

Abstract translation: 用于编程电熔丝的集成电路包括耦合到电熔丝的第一编程装置，用于选择性地为其提供第一编程电流;以及耦合到电熔丝的第二编程装置，用于选择性地将其提供给第二编程电流。 检测模块耦合到电熔丝，用于产生指示电熔丝的电阻电平的输出，其中电阻电平具有三个或更多个预定状态，这些状态通过用第一或第二编程电流选择性地编程电熔丝来提供。

公开(公告)号：US07468903B2

公开(公告)日：2008-12-23

申请号：US11598385

申请日：2006-11-13

Applicant: Dao-Ping Wang ,  Hung-Jen Liao ,  Kun Lung Chen ,  Yung-Lung Lin ,  Jui-Jen Wu ,  Chen Yen-Huei

Inventor： Dao-Ping Wang ,  Hung-Jen Liao ,  Kun Lung Chen ,  Yung-Lung Lin ,  Jui-Jen Wu ,  Chen Yen-Huei

IPC: G11C11/00

CPC classification number: G11C11/412 ,  G11C8/08 ,  G11C11/413 ,  G11C11/418

Abstract: A system and method for writing a SRAM cell coupled to complimentary first and second bit-lines (BLs) is disclosed, the method comprising asserting a word-line (WL) selecting the SRAM cell to a first positive voltage, providing a second positive voltage at the first BL, providing a first negative voltage at the second BL, and asserting a plurality of WLs not selecting the SRAM cell to a second negative voltage, wherein the writing margin of the SRAM cell is increased.

公开(公告)号：US20080137449A1

公开(公告)日：2008-06-12

申请号：US11636173

申请日：2006-12-08

Applicant: Jui-Jen Wu ,  Kun-Lung Chen ,  Hung-Jen Liao ,  Yung-Lung Lin ,  Chen Yen-Huei ,  Dao-Ping Wang

Inventor： Jui-Jen Wu ,  Kun-Lung Chen ,  Hung-Jen Liao ,  Yung-Lung Lin ,  Chen Yen-Huei ,  Dao-Ping Wang

IPC: G11C7/00

CPC classification number: G11C11/413

Abstract: A writing dynamic power control circuit is disclosed, which comprises a BL and its complementary BLB, at least one memory cell coupled to both the BL and BLB, a first NMOS transistor having a source, a drain and a gate coupled to the BL, the Vss and a first data signal, respectively, a second NMOS transistor having a source, a drain and a gate coupled to the BLB, the Vss and a second data signal, respectively, wherein the second data signal is complementary to the first data signal, a first PMOS transistor having a source, a drain and a gate coupled to a high voltage power supply (CVDD) node, the BLB and the BL, respectively, and a second PMOS transistor having a source, a drain and a gate coupled to the CVDD node, the BL and the BLB, respectively.

Abstract translation: 公开了一种写入动态功率控制电路，其包括BL及其互补BLB，耦合到BL和BLB的至少一个存储单元，具有耦合到BL的源极，漏极和栅极的第一NMOS晶体管， Vss和第一数据信号，分别具有耦合到BLB的源极，漏极和栅极的第二NMOS晶体管，Vss和第二数据信号，其中第二数据信号与第一数据信号互补， 第一PMOS晶体管，具有源极，漏极和栅极，分别耦合到高电压电源（CVDD）节点，BLB和BL，以及第二PMOS晶体管，其具有源极，漏极和栅极耦合到 CVDD节点，BL和BLB。

公开(公告)号：US08675418B2

公开(公告)日：2014-03-18

申请号：US12872135

申请日：2010-08-31

Applicant: Jui-Jen Wu ,  Shau-Wei Lu ,  Robert Lo ,  Kun-Hsi Li

Inventor： Jui-Jen Wu ,  Shau-Wei Lu ,  Robert Lo ,  Kun-Hsi Li

IPC: G11C7/10

CPC classification number: G11C7/10 ,  G11C7/1015 ,  G11C11/412 ,  G11C11/413

Abstract: A memory includes a memory cell, two word lines coupled to the memory cell, two bit lines coupled to the memory cell, and a write assist cell. The write assist cell is configured to transfer data of one bit line in a write operation to the other bit line in a read operation when one word line is used for the write operation, the other word line is used for the read operation, and the two word lines are asserted simultaneously.

Abstract translation: 存储器包括存储器单元，耦合到存储器单元的两个字线，耦合到存储器单元的两个位线以及写入辅助单元。 写入辅助单元被配置为当一个字线用于写入操作时，在读取操作中将写入操作中的一个位线的数据传送到另一个位线，另一个字线用于读取操作，并且 两个字线同时被断言。

公开(公告)号：US08462540B2

公开(公告)日：2013-06-11

申请号：US13284532

申请日：2011-10-28

Applicant: Meng-Fan Chang ,  Lai-Fu Chen ,  Jui-Jen Wu ,  Hiroyuki Yamauchi

Inventor： Meng-Fan Chang ,  Lai-Fu Chen ,  Jui-Jen Wu ,  Hiroyuki Yamauchi

IPC: G11C11/412

CPC classification number: G11C11/412

Abstract: A static random access memory cell comprising a first inverter, a second inverter, a first transistor, a second transistor, and a third transistor. The first inverter is cross-coupled with the second inverter. The first transistor is connected with a write word line, a write bit line, and a first output node of the first inverter. The second transistor is connected with a complementary write bit line, the write word line, and a second output node of the second inverter. The third transistor is connected with a read bit line, a read word line, and the first input node of the first inverter to form a read port transistor, and a read port is formed. The read port transistor has a feature of asymmetric threshold voltage, and the read bit line swing can be expanded by the decrease of clamping current or the boosted read bit line.

Abstract translation: 一种静态随机存取存储单元，包括第一反相器，第二反相器，第一晶体管，第二晶体管和第三晶体管。 第一个反相器与第二个反相器交叉耦合。 第一晶体管与第一反相器的写字线，写位线和第一输出节点连接。 第二晶体管与第二反相器的互补写位线，写字线和第二输出节点连接。 第三晶体管与读位线，读字线和第一反相器的第一输入节点连接，形成读端口晶体管，形成读端口。 读端口晶体管具有不对称阈值电压的特征，并且可以通过钳位电流或升压读位线的减小来扩展读位线摆幅。

公开(公告)号：US08233330B2

公开(公告)日：2012-07-31

申请号：US12347140

申请日：2008-12-31

Applicant: Jui-Jen Wu ,  Yi-Tzu Chen

Inventor： Jui-Jen Wu ,  Yi-Tzu Chen

IPC: G11C7/00

CPC classification number: G11C7/18 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/413

Abstract: A static random access memory (SRAM) circuit includes a pair of complementary global bit-lines, and a pair of complementary local bit-lines. A global read/write circuit is coupled to, and configured to write a small-swing signal to, the pair of global bit-lines in a write operation. The SRAM circuit further includes a first multiplexer and a second multiplexer, each having a first input and a second input. The first input of the first multiplexer and the first input of the second multiplexer are coupled to different one of the pair of global bit-lines. A sense amplifier includes a first input coupled to an output of the first multiplexer, and a second input coupled to an output of the second multiplexer. The sense amplifier is configured to amplify the small-swing signal to a full-swing signal, and outputs the full-swing signal to the pair of local bit-lines in the write operation.

Abstract translation: 静态随机存取存储器（SRAM）电路包括一对互补的全局位线和一对互补局部位线。 在写入操作中，全局读/写电路耦合到并配置成将小摆动信号写入该对全局位线。 SRAM电路还包括第一多路复用器和第二多路复用器，每个具有第一输入和第二输入。 第一多路复用器的第一输入和第二多路复用器的第一输入耦合到该对全局位线中的不同的一个。 读出放大器包括耦合到第一多路复用器的输出的第一输入和耦合到第二多路复用器的输出的第二输入。 读出放大器被配置为将小摆动信号放大到全摆幅信号，并且在写入操作中将全摆幅信号输出到一对局部位线。